mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 335

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mc68hc708mp16

Manufacturer Part Number
mc68hc708mp16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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16.4 I/O Signals
16.4.1 CGMXCLK
16.4.2 COPCTL Write
16.4.3 Power-On Reset
MC68HC708MP16
Freescale Semiconductor
NOTE:
Rev. 3.1
The COP counter is a free-running 6-bit counter preceded by the 13-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2
period is 53.3 ms. Writing any value to location $FFFF before overflow
occurs clears the COP counter and prevents reset.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR) (see
Status
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
The following paragraphs describe the signals shown in
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
Writing any value to the COP control register (COPCTL) (see
Control
of the SIM counter. Reading the COP control register returns the reset
vector.
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096
CGMXCLK cycles after power-up.
18
– 2
4
Register).
CGMXCLK cycles. With a 4.9152-MHz crystal, the COP timeout
Computer Operating Properly (COP)
Register) clears the COP counter and clears bits 12 through 4
Computer Operating Properly (COP)
7.7.3 SIM Reset
Figure
Technical Data
16.5 COP
16-1.
335

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