mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 349

• Manufacturer Part Number: mc68hc708mp16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

18.4.1 Polled LVI Operation
18.4.2 Forced Reset Operation
18.4.3 False Reset Protection
MC68HC708MP16
Freescale Semiconductor
Addr.
$FE0F
Name
LVI Status Register
—
Rev. 3.1
(LVISR)
In applications that can operate at V
software can monitor V
register, the LVIPWR bit must be at logic 0 to enable the LVI module, and
the LVIRST bit must be at logic 1 to disable LVI resets.
In applications that require V
enabling LVI resets allows the LVI module to reset the MCU when V
falls to the LVI
more consecutive CPU cycles. In the configuration register, the LVIPWR
and LVIRST bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
The V
supply noise. In order for the LVI module to reset the MCU,V
remain at or below the LVI
cycles. V
MCU out of reset.
Figure 18-2. LVI I/O Register Summary
Reset:
Read: LVIOUT
Write:
DD
DD
pin level is digitally filtered to reduce false resets due to power
Bit 7
must be above LVI
0
Low-Voltage Inhibit (LVI)
TRIPF
= Unimplemented
6
0
0
level and remains at or below that level for nine or
DD
by polling the LVIOUT bit. In the configuration
TRIPF
5
0
0
DD
TRIPR
to remain above the LVI
level for nine or more consecutive CPU
4
0
0
DD
for only one CPU cycle to bring the
levels below the LVI
3
0
0
Low-Voltage Inhibit (LVI)
2
0
0
TRIPF
Technical Data
TRIPF
1
0
0
DD
level,
must
level,
Bit 0
0
0
DD
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