mc68hc711d3 Freescale Semiconductor, Inc, mc68hc711d3 Datasheet - Page 109

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mc68hc711d3

Manufacturer Part Number
mc68hc711d3
Description
M Hc11 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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9.6 Control Timing
Freescale Semiconductor
Frequency of operation
E-clock period
Crystal frequency
External oscillator frequency
Processor control setup timet
Reset input pulse width
To guarantee external reset vector
Mode programming setup time
Mode programming hold time
Interrupt pulse width, PW
Wait recovery startup time
Timer pulse width PW
1. V
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
Minimum input time can be preempted by internal reset
IRQ edge-sensitive mode
Input capture pulse
Accumulator input
otherwise noted.
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to
Input/Output (I/O) Ports
DD
= 5.0 Vdc ± 10%, V
Notes:
PA0–PA3
PA0–PA3
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
1. Rising edge sensitive input
2. Falling edge sensitive input
PA7
PA7
(1) (3)
(2) (3)
(1)
(2)
TIM
Characteristic
(2)
IRQ
= t
SS
for further details.
cyc
= t
PCSU
= 0 Vdc, T
cyc
+ 20 ns
= 1/4 t
+ 20 ns
PW
(1)
TIM
A
cyc
= T
MC68HC711D3 Data Sheet, Rev. 2.1
+ 50 ns
L
Figure 9-3. Timer Inputs
to T
H
. All timing is shown with respect to 20% V
Symbol
PW
PW
PW
t
f
t
t
t
PCSU
4 f
XTAL
WRS
t
MPS
MPH
cyc
f
RSTL
O
IRQ
TIM
O
1000
1020
1020
Min
300
dc
dc
10
1.0 MHz
8
1
2
Max
1.0
4.0
4.0
4
Min
500
175
520
520
dc
dc
10
2.0 MHz
8
1
2
DD
and 70% V
Max
2.0
8.0
8.0
4
Min
333
133
353
353
dc
dc
10
3.0 MHz
8
1
2
Control Timing
DD
Chapter 5
, unless
Max
12.0
12.0
3.0
4
MHz
MHz
MHz
Unit
t
t
t
ns
ns
ns
ns
ns
cyc
cyc
cyc
109

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