mc68hc711d3 Freescale Semiconductor, Inc, mc68hc711d3 Datasheet - Page 33

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mc68hc711d3

Manufacturer Part Number
mc68hc711d3
Description
M Hc11 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 3
Central Processor Unit (CPU)
3.1 Introduction
This section presents information on M68HC11 central processor unit (CPU):
The CPU is designed to treat all peripheral, input/output (I/O), and memory locations identically as
addresses in the 64-Kbyte memory map. This is referred to as memory-mapped I/O. I/O has no
instructions separate from those used by memory. This architecture also allows accessing an operand
from an external memory location with no execution time penalty.
3.2 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory
locations. The seven registers, discussed in the following paragraphs, are shown in
Freescale Semiconductor
Architecture
Data types
Addressing modes
Instruction set
Special operations such as subroutine calls and interrupts
7
15
15
15
15
15
CONDITION CODE REGISTER
ACCUMULATOR A
DOUBLE ACCUMULATOR D
PROGRAM COUNTER
Figure 3-1. Programming Model
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
MC68HC711D3 Data Sheet, Rev. 2.1
0
7
7
S
X
ACCUMULATOR B
H
I
N
Z
V
C
0
0
0
0
0
0
0
A:B
D
IX
IY
SP
PC
CCR
CARRY
OVERFLOW
ZERO
NEGATIVE
I INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X INTERRUPT MASK
STOP DISABLE
Figure
3-1.
33

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