mc68hc68t1

Manufacturer Part Numbermc68hc68t1
DescriptionMc68hc68t1 Real-time Clock Plus Ram With Serial Interface
ManufacturerFreescale Semiconductor, Inc
mc68hc68t1 datasheet
 


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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Real-Time Clock plus RAM with
Serial Interface
CMOS
The MC68HC68T1 HCMOS Clock/RAM peripheral contains a real–time
clock/calendar, a 32 x 8 static RAM, and a synchronous, serial, three–wire
interface for communication with a microcontroller or processor. Operating in a
burst mode, successive Clock/RAM locations can be read or written using only
a single starting address. An on–chip oscillator allows acceptance of a
selectable crystal frequency or the device can be programmed to accept a
50/60 Hz line input frequency.
The LINE and system voltage (V SYS ) pins give the MC68HC68T1 the
capability for sensing power–up/power–down conditions, a capability useful for
battery–backup systems. The device has an interrupt output capable of
signaling a microcontroller or processor of an alarm, periodic interrupt, or power
sense condition. An alarm can be set for comparison with the seconds, minutes,
and hours registers. This alarm can be used in conjunction with the power
supply enable (PSE) output to initiate a system power–up sequence if the V SYS
pin is powered to the proper level.
A software power–down sequence can be initiated by setting a bit in the
interrupt control register. This applies a reset to the CPU via the CPUR pin, sets
the clock out (CLKOUT) and PSE pins low, and disables the serial interface.
This condition is held until a rising edge is sensed on the V SYS input pin,
signaling system power coming on, or by activation of a previously enabled
interrupt if the V SYS pin is powered up.
A watchdog circuit can be enabled that requires the microcontroller or
processor to toggle the slave select (SS) pin of the MC68HC68T1 periodically
without performing a serial transfer. If this condition is not met, the CPUR line
resets the CPU.
Full Clock Features — Seconds, Minutes, Hours (AM/PM), Day–of–Week,
Date, Month, Year (0 – 99), Auto Leap Year
32–Byte General Purpose RAM
Direct Interface to Motorola SPI and National MICROWIRE
Ports
Minimum Timekeeping Voltage: 2.2 V
Burst Mode for Reading/Writing Successive Addresses in Clock/RAM
Selectable Crystal or 50/60 Hz Line Input Frequency
Clock Registers Utilize BCD Data
Buffered Clock Output for Driving CPU Clock, Timer, Colon, or LCD
Backplane
Power–On Reset with First Time–Up Bit
Freeze Circuit Eliminates Software Overhead During a Clock Read
Three Independent Interrupt Modes — Alarm, Periodic, or Power–Down
CPU Reset Output — Provides Orderly Power–Up/Power–Down
Watchdog Circuit
Pin–for–Pin Replacement for CDP68HC68T1
Chip Complexity: 8500 FETs or 2125 Equivalent Gates
Also See Application Notes ANE425 “Use of the MC68HC68T1 RTC with
M6805 Microprocessor”, AN457 “Providing a Real–Time Clock for the
MC68302”, and AN1065 “Use of the MC68HC68T1 Real–Time Clock with
Multiple Time Bases”
MICROWIRE is a trademark of National Semiconductor Inc.
REV 2
2/96
MOTOROLA
Motorola, Inc. 1996
MC68HC68T1
16
1
16
1
ORDERING INFORMATION
MC68HC68T1P
MC68HC68T1DW SOG Package
PIN ASSIGNMENT
CLKOUT
1
CPUR
2
INT
3
SCK
4
MOSI
5
MISO
6
SS
7
V SS
8
t
Serial Data
Order this document
by MC68HC68T1/D
P SUFFIX
PLASTIC DIP
CASE 648
DW SUFFIX
SOG PACKAGE
CASE 751G
Plastic DIP
16
V DD
15
XTAL out
14
XTAL in
13
V BATT
12
V SYS
11
LINE
10
POR
9
PSE
MC68HC68T1
1

mc68hc68t1 Summary of contents

  • Page 1

    ... Hz line input frequency. The LINE and system voltage (V SYS ) pins give the MC68HC68T1 the capability for sensing power–up/power–down conditions, a capability useful for battery–backup systems. The device has an interrupt output capable of signaling a microcontroller or processor of an alarm, periodic interrupt, or power sense condition ...

  • Page 2

    ... INT LOGIC CONTROL REG 12 POWER V SYS SENSE 10 POR CONTROL 9 PSE 2 CPUR 4 SCK 6 MISO 5 MOSI 7 SS MC68HC68T1 2 BLOCK DIAGRAM SECOND MINUTE CLOCK SELECT CLOCK 8–BIT DATA BUS INTERRUPT COMPARATOR SECOND MINUTE LATCH LATCH STATUS REGISTER RAM SERIAL INTERFACE PIN PIN ...

  • Page 3

    ... Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Unused outputs must be left open Guaranteed V Limit Unit — 3.0 to 6.0 V — 2.2 V 3.0 0.9 V 4.5 1.35 6.0 1.8 3.0 2.1 V 4.5 3.15 6.0 4.2 5 p–p 4.5 0.1 V 0.4 4.5 4.4 V 3 6.0 – 1 6.0 100 5.0 0.1 mA 0.6 0.84 1.2 5.0 0.024 0.12 0.24 0 250 360 600 MC68HC68T1 3 ...

  • Page 4

    ... Minimum Pulse Width, POR Maximum Input Rise and Fall Times (Except XTAL in and POR) (Measured Between 70 and 20 MC68HC68T1 – 200 pF, Input ns, Voltages Referenced Parameter Parameter Figure V DD Guaranteed No ...

  • Page 5

    ... — — — — — — PLZ , t PHZ HIGH IMPEDANCE t TLH , t THL CONNECT WHEN TESTING t PLZ AND t PZL CONNECT WHEN TESTING t PHZ AND t PZH MC68HC68T1 5 ...

  • Page 6

    ... When Watchdog (bit 7) in the interrupt control register is set high, the clock’s slave select pin must be toggled at regu- lar intervals without a serial data transfer not toggled at the rate shown in Table 2, the MC68HC68T1 supplies a MC68HC68T1 6 CPU reset pulse at Pin 2 and Watchdog (bit 6) in the status register is set (see Figure 7) ...

  • Page 7

    ... An interrupt is not generated when the fourth method is utilized. While in the single–supply mode, power–up is initiated when the V SYS pin loses power and then returns high. There is no interrupt generated when using this method (see Fig- ure 11). MC68HC68T1 7 ...

  • Page 8

    ... BYTES GENERAL–PURPOSE USER RAM READ ADDRESSES ONLY CLOCK/CALENDAR READ ADDRESSES ONLY NOT USED 32 BYTES GENERAL–PURPOSE USER RAM WRITE ADDRESSES ONLY CLOCK/CALENDAR WRITE ADDRESSES ONLY MC68HC68T1 8 HEXADECIMAL $ DAY OF THE WEEK R DATE OF THE MONTH U $1F $ STATUS REGISTER CLOCK CONTROL REGISTER ...

  • Page 9

    ... HOURS (01 – – 23) DAY OF WEEK (01 – 07) SUNDAY = 1 DATE OF MONTH (01 – 31) MONTH (01 – 12) JAN = 1 YEAR (00 – 99) CLOCK CONTROL REGISTER INTERRUPT CONTROL REGISTER SECONDS ALARM (00 – 59) MINUTES ALARM (00 – 59) HOURS ALARM (01 – – 23) DB5 PM MODE STATUS REGISTER DATA MC68HC68T1 9 ...

  • Page 10

    ... Table 2. Watchdog Service and Reset Times Service Time Reset Time NOTE: Reset does not occur immediately after slave select is toggled. Approximately two clock cycles later, reset initiates. SS SCK CPUR MC68HC68T1 10 Function Decimal Range 0 – – – – – – ...

  • Page 11

    ... Figure 9. Software Power–Down Functional Diagram MOTOROLA XTAL in XTAL out INT V DD LINE REAL–TIME CLOCK MC68HC68T1 MSB LSB 1 (STATUS REGISTER) TO SYSTEM POWER CONTROL PSE LSB CLKOUT OSC RESET CPUR V SYS V BATT MISO MOSI MC68HC05C4 V DD IRQ MC68HC05C4 CPU CPU MC68HC68T1 11 ...

  • Page 12

    ... SIGNAL PSE ALARM CIRCUIT CPUR PERIODIC INTERRUPT CLKOUT SIGNAL POWER SENSE CIRCUIT SERIAL INTERFACE REAL–TIME CLOCK MC68HC68T1 V DD BACKUP PSE SWITCH POWER SWITCH/ MODE CONTROL CPUR CLKOUT V SYS SERIAL INTERFACE REAL–TIME CLOCK MC68HC68T1 MISO MOSI V BATT MISO MOSI MOTOROLA ...

  • Page 13

    ... At the end of the power–on reset, single–supply or battery–backup mode is selected at this time, determined by the state of V SYS . This pin may be more aptly named first–time–up reset. MC68HC68T1 13 ...

  • Page 14

    ... This pin is the only oscillator power source and should be connected to the positive terminal of the battery. The V BATT pin always supplies power to the MC68HC68T1, even when the device is not in the battery–backup mode. To maintain timekeeping, the V BATT pin must be at least 2.2 V. When the level on the V SYS pin falls below V BATT + 0 ...

  • Page 15

    ... Hz X 256 Hz X 128 LSB FIRST INTER- POWER ALARM CLOCK TIME– RUPT SENSE INT INT UP TRUE INT NOTE MC68HC68T1 15 ...

  • Page 16

    ... In systems using the MC68HC05C4 or MC68HC11A8, the inactive clock polarity is determined by the clock polarity (CPOL) bit in the microcomputer’s control register. A unique feature of the MC68HC68T1 is that the level of the inactive clock is determined by sampling SCK when SS MC68HC68T1 16 becomes active. Therefore, either SCK polarity is accom- modated ...

  • Page 17

    ... D0 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î LSB Î Î Î Î Î Î Î D0 Î Î Î Î Î Î Î MC68HC68T1 17 ...

  • Page 18

    ... LSB Additional reading or writing requires re–enabling the device A1 A0 and providing a new address byte. If the MC68HC68T1 is not disabled, additional bytes can be read or written in a burst mode. Each read or write cycle causes the Clock/Calendar register or RAM address to automatically increment. Incre- menting continues after each byte transfer until the device is disabled ...

  • Page 19

    ... APPLICATION CIRCUITS 100 kΩ NOTE POR 0 INT SYS LINE V DD MC68HC68T1 13 V BATT 2 CPUR NOTE SCK 5 MOSI 6 MISO XTAL in 14 Figure 18. Power–Always–On System IRQ 38 MC68HC05C4 1 RESET 34 PORT 33 SCK 32 MOSI 31 MISO MC68HC68T1 19 ...

  • Page 20

    ... NOTE 1 NOTES: 1. The LINE input pin can sense when the switch opens by use of the power sense interrupt. The MC68HC68T1 crystal drives the clock input to the CPU using the CLKOUT pin. On power–down when V SYS < V BATT + 0 BATT powers the clock. A threshold detect activates an on–chip P channel switch, connecting V BATT BATT always supplies power to the oscillator, keeping voltage frequency variation to a minimum ...

  • Page 21

    ... REGULATOR R CHARGE NOTE 1 NOTES: 1. See Figure 12 for 32.768 kHz operation. This configuration, where the MC68HC68T1 supplies the MCU clock, usually requires MHz crystal MC68HC11 MCU is used, delete the capacitor at the RESET pin. Figure 20. Rechargeable Battery–Backup System MOTOROLA NC 100 kΩ ...

  • Page 22

    ... Also, the CMOS CPU is not powered down with the system but is held in a low power reset mode during power–down. When restoring power, the MC68HC68T1 enables the CLKOUT pin and sets the PSE and CPUR pins high. ...

  • Page 23

    ... Figure 22. Non–Rechargeable Battery–Backup System MOTOROLA LIMIT D BLOCK W 100 BATT SYS 11 LINE 6 10 POR MISO 5 W MOSI 215 XTAL out INT SCK 14 XTAL in MC68HC68T1 1 CLKOUT 2 9 CPUR PSE 0 pF* 32.768 kHz 10 pF* MC68HC68T1 23 ...

  • Page 24

    ... The clock loses time, but the oscillator is tuned. Do not make constant accesses to the clock. When a read or write cycle is started, the clock stops incrementing time. MC68HC68T1 24 4. When the part is power cycled, the clock loses all time and data. Check the battery installation and ensure that a diode is in the circuit from Can a non– ...

  • Page 25

    ... DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 10.15 10.45 0.400 0.411 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 MC68HC68T1 25 ...

  • Page 26

    ... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 *MC68HC68T1/D* MC68HC68T1/D MOTOROLA ...