mc68hc68t1 Freescale Semiconductor, Inc, mc68hc68t1 Datasheet - Page 15

• Manufacturer Part Number: mc68hc68t1
• Description: Mc68hc68t1 Real-time Clock Plus Ram With Serial Interface
• Manufacturer: Freescale Semiconductor, Inc

operation. Consult crystal manufacturer for R1 value for oth-
er frequencies. Resistor R2 must be used in 32 kHz opera-
tion only. Use a 200 to 300 k
oscillator until the control register is set properly and reduces
standby current.
50 Hz – 60 Hz
put when this bit is set high; a low accommodates 60 Hz. The
power sense bit in the interrupt control register must be reset
low for line frequency operation.
Clock Out
as the square–wave clock output (CLKOUT).
reset. Therefore, XTAL is selected as the clock output at this
time.
INTERRUPT CONTROL REGISTER (READ/WRITE) —
READ ADDRESS $32/WRITE ADDRESS $B2
Watchdog
abled. This function requires the CPU to toggle the SS pin
periodically without a serial transfer requirement. In the event
this does not occur, a CPU reset is issued at the CPUR pin.
The status register must be read before re–enabling the
watchdog function.
Power–Down
occurs via the CPUR output, the CLKOUT and PSE output
pins are reset low, and the serial interface is disabled.
Power Sense
to sense a power failure. When power sense is selected, the
input to the 50/60 Hz prescaler is disconnected; therefore,
crystal operation is required. An interrupt is generated when
a power failure is sensed and the power sense and interrupt
true bit in the status register are set. When power sense is
activated, a logic low must be written to this location followed
by a high to re–enable power sense.
MOTOROLA
Resistor R1 is recommended to be 10 M
50 Hz may be used as the input frequency at the LINE in-
Three bits specify one of the seven frequencies to be used
All bits in the clock control register are reset by a power–on
When this bit is set high, the watchdog operation is en-
A high in this location initiates a power–down. A CPU reset
When set high, this bit is used to enable the LINE input pin
All bits are reset low by power–on reset.
WATCH–
MSB
DOG
D7
0 = XTAL
1 = XTAL/2
2 = XTAL/4
3 = XTAL/8
POWER–
DOWN
D6
POWER
SENSE
D5
4 = Disable (low output)
5 = 1 Hz
6 = 2 Hz
7 = 50/60 Hz for LINE operation
7 = 64 Hz for XTAL operation
ALARM
D4
W
range. This stabilizes the
D3
PERIODIC SELECT
D2
W
D1
for 32 kHz
LSB
D0
Alarm
bit is set high. When an equal comparison occurs between
the seconds, minutes, and hours time counters and alarm
latches, the interrupt output is activated. When loading the
time counters, this bit should be reset low to avoid a false in-
terrupt. This is not required when loading the alarm latches.
See INT pin description for explanation of alarm delay.
Periodic Select
the frequency of the periodic output (see Table 3).
STATUS REGISTER (READ ONLY) — ADDRESS $30
Watchdog
CPU failure.
First Time–Up
the RAM and Clock is not valid and should be initialized.
MSB
D7
0
The output of the alarm comparator is enabled when this
The value in these four bits (D0, D1, D2, and D3) selects
If this bit is set high, the watchdog circuit has detected a
Power–on reset sets this bit high. This signifies the data in
D3 – D0
Table 3. Periodic Interrupt Output Frequencies
Value
Value
(Hex)
WATCH–
All bits are reset low by a power–on reset except
the first time–up bit which is set high. All bits ex-
cept the power sense bit are reset after a read of
the status register.
DOG
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
D6
Output Frequency
D5
Periodic Interrupt
Periodic Interrupt
1 Cycle per Minute
0
1 Cycle per Hour
1 Cycle per Day
50 or 60 Hz
TIME–
FIRST
2048 Hz
1024 Hz
Disable
512 Hz
256 Hz
128 Hz
UP
D4
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
(at INT Pin)
INTER-
NOTE
RUPT
TRUE
D3
POWER
Frequency Timebase
SENSE
INT
XTAL
D2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MC68HC68T1
ALARM
INT
D1
Line
X
X
X
X
X
X
CLOCK
LSB
D0
INT
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