mc68hc68t1 Freescale Semiconductor, Inc, mc68hc68t1 Datasheet - Page 16

• Manufacturer Part Number: mc68hc68t1
• Description: Mc68hc68t1 Real-time Clock Plus Ram With Serial Interface
• Manufacturer: Freescale Semiconductor, Inc

After the status register is read, the first time–up bit is set low
if the POR pin is high. Conversely, if the POR pin is held low,
the first time–up bit remains set high.
Interrupt True
(power sense, alarm, or clock) is valid.
Power–Sense Interrupt
generated an interrupt. This bit is not reset after a read of this
register.
Alarm Interrupt
time counters and alarm latches are equal, this bit is set high.
The status register must be read before loading the interrupt
control register for valid alarm indication after the alarm acti-
vates.
Clock Interrupt
MC68HC68T1 is a serial synchronous bus for address and
data transfers. The shift clock (SCK), which is generated by
the microcomputer, is active only during address and data
transfer. In systems using the MC68HC05C4 or
MC68HC11A8, the inactive clock polarity is determined by
the clock polarity (CPOL) bit in the microcomputer’s control
register.
the inactive clock is determined by sampling SCK when SS
MC68HC68T1
16
A high in this bit signifies that one of the three interrupts
This bit set high signifies that the power–sense circuit has
When the contents of the seconds, minutes, and hours
A periodic interrupt sets this bit high (see Table 3).
The serial peripheral interface (SPI) utilized by the
A unique feature of the MC68HC68T1 is that the level of
SERIAL PERIPHERAL INTERFACE (SPI)
becomes active. Therefore, either SCK polarity is accom-
modated. Input data (MOSI) is latched internally on the inter-
nal strobe edge and output data (MISO) is shifted out on the
shift edge (see Table 4 and Figure 13). There is one clock for
each bit transferred. Address as well as data bits are trans-
ferred in groups of eight.
* MISO remains at a High–Z until eight bits of data are ready to be
ADDRESS AND DATA FORMAT
serial data input (MOSI) and out of the serial data output
(MISO). Any transfer of data requires the address of the byte
to specify a write or read Clock or RAM location, followed by
one or more bytes of data. Data is transferred out of MISO for
a read operation and into MOSI for a write operation (see
Figures 14 and 15).
shifted out during a read. MISO remains at a High–Z during the entire
write cycle.
Disabled
There are three types of serial transfers:
The address and data bytes are shifted MSB first, into the
Mode
Mode
Reset
Read
Write
1. Read or write address
2. Read or write data
3. Watchdog reset (actually a non–transfer)
SS
H
H
L
Table 4. Function Table
CPOL = 1
CPOL = 0
CPOL = 1
CPOL = 0
Disabled
Input
SCK
Signal
Disabled
Data Bit
MOSI
Latch
Input
X
MOTOROLA
Next Data
Bit Shifted
High–Z
High–Z
MISO
Out*