ng80960kb-25 Intel Corporation, ng80960kb-25 Datasheet
ng80960kb-25
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ng80960kb-25 Summary of contents
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... Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ trademark of Digital Equipment Corporation) Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. ...
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THE i960® PROCESSOR The 80960KB is a member of the 32-bit architecture from Intel known as the i960 processor family. These were especially designed to serve the needs of embedded applications. The embedded market includes applications as diverse as ...
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Key Performance Features The 80960 architecture is based on the most recent advances in microprocessor technology and is grounded in Intel’s long experience in the design and manufacture of embedded microprocessors. Many features contribute to the 80960KB’s exceptional performance: ...
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Table 1. 80960KB Instruction Set Data Movement Arithmetic Load Add Store Subtract Move Multiply Load Address Divide Remainder Modulo Shift Comparison Branch Compare Unconditional Branch Conditional Compare Conditional Branch Compare and Increment Compare and Branch Compare and Decre- ment Debug ...
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Opcode Control Compare and Opcode Reg/Lit Branch Register to Opcode Register Memory Access— Opcode Short Memory Access— Opcode Long 1.1.1. Memory Space And Addressing Modes The 80960KB offers a linear programming environ- ment so that all programs running on the ...
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FP3). These registers perform the same function as the general-purpose registers provided in other popular microprocessors. The term global refers to the fact that these registers retain their contents across procedure calls. The local registers, on ...
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REGISTER CACHE ONE OF FOUR LOCAL REGISTER SETS Figure 4. Multiple Register Sets Are Stored On-Chip 1.1.7. Floating-Point Arithmetic In the 80960KB, floating-point arithmetic has been made an integral part of the architecture. Having the floating-point unit integrated on-chip provides ...
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Interrupt Handling The 80960KB can be interrupted in two ways: by the activation of one of four interrupt pins or by sending a message on the processor’s data bus. The 80960KB is unusual in that it automatically handles interrupts ...
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Table 4. 80960KB Pin Description: L-Bus Signals (Sheet NAME TYPE CLK2 I SYSTEM CLOCK provides the fundamental timing for 80960KB systems divided by two inside the 80960KB and four 80-bit registers (FP0 through FP3) to ...
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Table 4. 80960KB Pin Description: L-Bus Signals (Sheet NAME TYPE BE3:0 O BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are used in the current bus cycle. BE3 corresponds to LAD31:24; ...
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Table 5. 80960KB Pin Description: Support Signals (Sheet NAME TYPE FAILURE O INITIALIZATION FAILURE indicates that the processor did not initialize correctly. After RESET deasserts and before the first bus transaction begins, FAILURE asserts O.D. while the ...
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Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance is reduced by shortening board traces between the processor and decoupling capacitors as much as possible. 2.3. Connection Recommendations For reliable operation, always connect unused inputs ...
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360 340 320 25 MHz 300 20 MHz 16 MHz 280 260 240 220 200 -60 -40 -20 0 CASE TEMPERATURE (°C) Figure 7. Typical Supply Current vs. Case Temperature 400 TEMP = ...
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TEMP = +22°C 360 @5.5V 340 @5.0V 320 @4.5V 300 280 260 240 220 200 180 160 Figure 9. Typical Current vs. Frequency (Hot Temp) (TEMP = +85° 4.5V) CC 0.8 0.6 0.4 0.2 0 ...
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Test Load Circuit Figure 12 illustrates the load circuit used to test the 80960KB’s three-state pins; Figure 13 shows the load circuit used to test the open drain outputs. The open drain test uses an active load circuit in ...
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Absolute Maximum Ratings Operating Temperature (PGA).............. 0°C to +85°C Cas e (PQFP) ......... 0°C to +100°C Cas e Storage Temperature ................................. –65°C to +150° C Voltage on Any Pin................................. –0. Power Dissipation .......................................... 2.5W (25 MHz) 2.7. ...
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AC Specifications This section describes the AC specifications for the 80960KB pins. All input and output timings are specified relative to the 1.5 V level of the rising edge of CLK2. For output timings the specifications refer to the ...
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AC Specification Tables Table 7. 80960KB AC Characteristics (16 MHz) Symbol Parameter Input Clock T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time 3 (CLK2) T Processor Clock Fall Time ...
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Table 8. 80960KB AC Characteristics (20 MHz) Symbol Parameter Input Clock T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time 3 (CLK2) T Processor Clock Fall Time (CLK2 Processor ...
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Table 9. 80960KB AC Characteristics (25 MHz) Symbol Parameter Input Clock T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time 3 (CLK2) T Processor Clock Fall Time (CLK2 Processor ...
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HIGH LEVEL (MIN) 0.55V CC 1.5 V 10% LOW LEVEL (MAX) 0. Figure 15. Processor Clock Pulse (CLK2) ... CLK2 ... CLK ... RESET T 17 ... OUTPUTS INIT PARAMETERS (BADAC, INT /IAC) MUST BE SET UP 8 ...
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MECHANICAL DATA 3.1. Packaging The 80960KB is available in two package types: • 132-lead ceramic pin-grid array (PGA). Pins are arranged 0.100 inch (2.54 mm) center-to-center matrix, three rows around (see Figure 17). • ...
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P V N.C. N.C. N.C. N.C. N. N.C. N.C. N.C. N.C. N. N.C. N.C. N. DEN N. FAIL V ...
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N.C. N.C. N.C. N. N.C. N.C. N.C. N.C. N.C. N. N.C. N.C. N. N.C. N. N.C. N.C. V ...
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LAD0 100 LAD1 101 LAD2 102 V ...
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Pinout Table 10. 80960KB PGA Pinout — In Pin Order Pin Signal Pin LAD LAD SS A3 LAD C8 LAD 19 A4 LAD C9 LAD 17 A5 LAD C10 ...
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Table 11. 80960KB PGA Pinout — In Signal Order Signal Pin Signal ADS D2 LAD 15 ALE D1 LAD 16 BADAC C3 LAD LAD LAD LAD ...
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Table 12. 80960KB PQFP Pinout — In Pin Order Pin Signal Pin 1 HLDA 34 N.C. 2 ALE LAD LAD 37 N. LAD 38 N. LAD 39 N.C. 29 ...
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Table 13. 80960KB PQFP Pinout — In Signal Order Signal Pin Signal ADS 132 LAD 15 ALE 2 LAD 16 BADAC 129 LAD LAD LAD LAD ...
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Package Thermal Specification The 80960KB is specified for operation when case temperature is within the range 0°C to 85°C (PGA) or 0°C to 100°C (PQFP). Measure case temperature at the top center of the package. Ambient temperature can be ...
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Table 15. 80960KB PQFP Package Thermal Characteristics Thermal Resistance — °C/Wat t Airflow — ft./min (m/sec) Parameter 0 50 100 (0) (0.25) (0.50) Junction-to-Case Case-to-Ambient (No Heatsink) NOTES: 1. This table applies to 80960KB ...
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AIRFLOW (ft/min) PQFP PGA with no PGA with omni- PGA with uni- heatsink directional heatsink directional heatsink Figure 23. 16 MHz Maximum Allowable Ambient Temperature 90 85 ...
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AIRFLOW (ft/min) PQFP PGA with no PGA with omni- heatsink directional heatsink Figure 25. 25 MHz Maximum Allowable Ambient Temperature 120 115 110 105 ...
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WAVEFORMS Figures 27, 28, 29 and 30 show the waveforms for various transactions on the 80960KB’s local bus CLK2 CLK LAD31:0 ALE ADS BE3:0 W/R DT/R DEN READY Figure 27. Non-Burst Read and Write Transactions Without Wait ...
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CLK2 CLK LAD31:0 ALE ADS BE3:0 W/R DT/R DEN READY Figure 28. Burst Read and Write Transaction Without Wait States 80960KB ...
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CLK2 CLK LAD31:0 ALE ADS BE3:0 W/R DT/R DEN READY Figure 29. Burst Write Transaction with Wait States 80960KB ...
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CLK2 CLK LAD31:0 ALE ADS BE3:2 BE1:0 W/R DT/R DEN READY Figure 30. Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word Boundary ( Wait States) ...
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PREVIOUS INTERRUPT CYCLE ACKNOWLEDGEMENT CYCLE CLK2 CLK INTR LAD31:0 ADDR ALE ADS INTA DT/R DEN LOCK READY NOTE: INTR can go low no sooner than the input hold time following the ...
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REVISION HISTORY No revision history was maintained in earlier revisions of this data sheet. All errata that has been identified to date is incorporated into this revision. The sections significantly changed since the previous revision are: Section Table 4. ...