pal22v10-7 Advanced Micro Devices, pal22v10-7 Datasheet

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pal22v10-7

Manufacturer Part Number
pal22v10-7
Description
Pal22v10 Family, Ampal22v10/a 24-pin Ttl Versatile Pal Device
Manufacturer
Advanced Micro Devices
Datasheet

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PAL22V10 Family, AmPAL22V10/A
24-Pin TTL Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The PAL22V10 provides user-programmable logic for
replacing conventional SSI/MSI gates and flip-flops at a
reduced chip count.
The PAL22V10 device implements the familiar Boolean
logic transfer function, the sum of products. The PAL de-
vice is a programmable AND array driving a fixed OR
array. The AND array is programmed to create custom
product terms, while the OR array sums selected terms
at the outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to 16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
BLOCK DIAGRAM
Publication# 16559
Issue Date: February 1996
As fast as 7.5-ns propagation delay and
91 MHz f
10 Macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
Varied product term distribution allows up to
16 product terms per output for complex
functions
RESET
OUTPUT
MACRO
LOGIC
CELL
FINAL
I/O
MAX
8
0
Rev. C
1
(external)
OUTPUT
CLK/I
MACRO
LOGIC
CELL
I/O
Amendment /0
10
1
0
OUTPUT
MACRO
LOGIC
CELL
I/O
12
COM’L: -7/10/15
2
OUTPUT
MACRO
LOGIC
CELL
I/O
14
3
OUTPUT
MACRO
LOGIC
Programmable
CELL
I/O
16
AND Array
(44 x 132)
4
OUTPUT
MACRO
grammed as registered or combinatorial, and active
high or active low. The output configuration is
determined by two fuses controlling two multiplexers in
each macrocell.
AMD’s FusionPLD program allows PAL22V10 designs
to be implemented using a wide variety of popular indus-
try-standard design tools. By working closely with the
FusionPLD partners, AMD certifies that the tools pro-
vide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
LOGIC
CELL
I/O
16
Global asynchronous reset and synchronous
preset for initialization
Power-up reset for initialization and register
preload for testability
Extensive third-party software and programmer
support through FusionPLD partners
24-Pin SKINNYDIP, 24-pin Flatpack and
28-pin PLCC and LCC packages save space
5
OUTPUT
MACRO
LOGIC
CELL
I/O
14
6
OUTPUT
MACRO
LOGIC
CELL
I/O
12
7
OUTPUT
MACRO
LOGIC
CELL
I/O
11
10
8
I
1
- I
11
OUTPUT
MACRO
LOGIC
Advanced
CELL
I/O
8
9
Devices
16559C-1
Micro
PRESET
2-197

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pal22v10-7 Summary of contents

Page 1

... The PAL22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The PAL22V10 device implements the familiar Boolean logic transfer function, the sum of products. The PAL de- vice is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs ...

Page 2

... Input/Output Connect V = Supply Voltage CC 2-198 V CC I 16559C-2 PAL22V10 Family PLCC/LCC I I/O I 16559C ...

Page 3

... Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. PAL22V10-7/10/15, AmPAL22V10A (Com’l) AMD OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +75 C) ...

Page 4

... HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. The PAL22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four potential out- put configurations; registered output or combinatorial I/O, active high or active low (see Figure 2). The configu- ration choice is made according to the user’ ...

Page 5

... Registered Output Configuration Each macrocell of the PAL22V10 includes a D-type flip- flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock in- put. In the registered configuration (S feedback is from Q of the flip-flop CLK SP Registered/Active Low CLK ...

Page 6

... Approved programmers are listed at the end of this data book. 2-202 Quality and Testability The PAL22V10 offers a very high level of built-in quality. Extra programmable fuses, test words and test columns provide a means of verifying performance of all AC and DC parameters. In addition, this verifies complete ...

Page 7

... (13 GND 12 (14 PAL22V10 Family AMD 24 (28 (27 ...

Page 8

... OUT (Note 0 Max (Note 3) OUT Outputs Open ( Max CC and I (or I and OZL IH OZH PAL22V10-7 (Com’ + +4. +5.25 V Min Max 2.0 0.8 –1.2 25 Input –100 CLK –150 1 100 – ...

Page 9

... CF = 1/f MAX (internal feedback) – Test Conditions 2.0 V OUT MHz 1/( 1/( (Note 6) CNT S CF 1/( PAL22V10-7 (Com’l) AMD Typ Unit Min (Note 3) Max Unit 1 7 ...

Page 10

... OUT (Note 0 Max (Note 3) OUT Outputs Open ( Max CC and I (or I and OZL IH OZH PAL22V10-10 (Com’ + +4. +5.25 V Min Max 2.0 0.8 –1.2 25 –100 Input –150 CLK 1 100 – ...

Page 11

... CF = 1/f MAX (internal feedback) – Test Conditions 2.0 V OUT MHz 1/( 1/( (Note 5) CNT S CF 1/( PAL22V10-10 (Com’l) AMD Typ Unit Min (Note 3) Max Unit ...

Page 12

... OUT (Note 0 Max (Note 3) OUT Outputs Open ( Max CC and I (or I and OZL IH OZH PAL22V10-15 (Com’ + +4. +5.25 V Min Max 2.0 0.8 –1.2 25 –100 1 100 –100 –30 – ...

Page 13

... CF = 1/f MAX (internal feedback) – Test Conditions MHz V = 2.0 V OUT 1/( 1/( (Note 5) CNT S CF 1/( PAL22V10-15 (Com’l) AMD Typ Unit Min (Note 3) Max Unit ...

Page 14

... OUT (Note 0 Max (Note 3) OUT Outputs Open ( Max CC and I (or I and OZL IH OZH AmPAL22V10A (Com’ + +4. +5.25 V Min Max 2.0 0.8 –1.2 25 –100 1 100 –100 –30 – ...

Page 15

... These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. Test Conditions MHz V = 2.0 V OUT 1/( AmPAL22V10A (Com’l) AMD Typ Unit Min Max Unit ...

Page 16

... PD Registered V T Output 16559C-7 Input or Feedback V T Output t WL 16559C-9 Input Asserting Synchronous V T Preset V Clock T t ARR Registered V T Output 16559C-11 PAL22V10 Family 16559C-8 Registered Output 0. 0.5V OL 16559C-10 ...

Page 17

... Apply Line is High- Impedance “Off” State KS000010-PAL Output Commercial 300 5 pF PAL22V10 Family AMD Test Point 16559C-13 Measured R Output Value 2 All except -7: 1.5 V 390 1 – 0 300 0 2-213 ...

Page 18

... AMD MEASURED SWITCHING CHARACTERISTICS for the PAL22V10- 4. (Note Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where t PD may be affected. ...

Page 19

... INPUT/OUTPUT EQUIVALENT SCHEMATICS Input Program/Verify Circuitry Typical Input 40 NOM Input, I/O Pins Typical Output PAL22V10 Family AMD V CC 16559C- Output Program/Verify/ Test Circuitry Preload Circuitry 16559C-17 2-215 ...

Page 20

... CC Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feed- back setup times are met Power-Up Reset Waveform PAL22V10 Family Max Unit 1000 ns See Switching Characteristics V CC 16559C-18 ...

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