palce20v8h-15pi Lattice Semiconductor Corp., palce20v8h-15pi Datasheet
palce20v8h-15pi
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palce20v8h-15pi Summary of contents
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DISTINCTIVE CHARACTERISTICS Pin and function compatible with all PAL Electrically erasable CMOS technology provides reconfigurable logic and full testability High-speed CMOS technology — 5-ns propagation delay for “-5” version — 7.5-ns propagation delay for “-7” version Direct plug-in replacement for ...
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The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. ...
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This file, once downloaded to a programmer, configures the device according to the user’s desired function. The user is given two design options with the PALCE20V8. First, it ...
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CONFIGURATION OPTIONS Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial I/O or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the ...
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Dedicated Input in a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 0 and SL0 feedback signal is an adjacent I/O pin. Combinatorial I Non-Registered Device The control settings are SG0 = 1, SG1 ...
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CLK a. Registered active Low c. Combinatorial I/O active low Combinatorial output active low Notes: 1. Feedback is not available on pins 18 (21) and 19 (23) in the combinatorial output mode. 2. ...
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... PCI Compliance PALCE20V8H devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The PALCE20V8H’s predictable timing ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent upon routing and product term distribution ...
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LOGIC DIAGRAM CLK ( ( ( ( (6) 24 ...
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LOGIC DIAGRAM (CONTINUED ( (10 ...
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... 0 Max (Note 3) OUT CC Outputs Open ( mA), V OUT V = Max CC Outputs Open ( mA), OUT V = Max MHz CC and I (or I and I ). OZL IH OZH PALCE20V8H-5/7/10 (Com’l) ) Operating Min Max , V = Min 2 Min 0.5 CC 2.0 0.8 10 –100 10 –100 –30 –150 = 125 ...
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... Future process improvements PZX PXZ EA ER can be found using the following equation: CF PALCE20V8H-5/7/10 (Com’l) Typ Unit 5 pF ° 5 MHz - Min Max Min ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...
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CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...
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... Max OUT (Note 0 Max (Note 3) OUT CC Outputs Open ( mA), OUT V = Max MHz CC and I (or I and I ). OZL IH OZH PALCE20V8H-15/25 Q-15/25 (Com’l) ) Operating Min Max = Min 2 Min 0.5 CC 2.0 0.8 10 –100 10 –100 –30 –150 Unit µ ...
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... CF MAX S Test Conditions 2 OUT = 2.0 V 1/( 1/( (Note 3) CNT S CF 1/( can be found using the following equation: CF PALCE20V8H-15/25 Q-15/25 (Com’l) Typ Unit 5 pF ° 5 MHz 8 pF -15 -25 Min Max Min Max Unit ...
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... Max , OUT 0 Max (Note 3) OUT CC Outputs Open ( mA), OUT V = Max MHz CC and I (or I and I ). OZL IH OZH PALCE20V8H-15/25 Q-20/25 (ind) ) Operating Min Max Unit 2.4 0.5 2.0 0.8 10 –100 (Note (Note 2) –100 IL –30 –150 H 130 µ ...
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... Min Max 1/( 45 1/( (Note 1/( 62 can be found using the following equation: CF PALCE20V8H-15/25 Q-20/25 (ind) Typ Unit 5 pF ° -20 -25 Min Max Min Max Unit ...
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SWITCHING WAVEFORMS Input or V Feedback Combinatorial Output a. Combinatorial output t WH Clock c. Clock width OE Output Notes 1 Input pulse amplitude 3 Input ...
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KEY TO SWITCHING WAVEFORMS WAVEFORM SWITCHING TEST CIRCUIT 5 V Output Specification Closed Open PZX Closed H Z: Open PXZ ER L ...
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TYPICAL I CHARACTERISTICS 25° 150 125 100 The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, ...
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ENDURANCE CHARACTERISTICS The PALCE20V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts result, the device can be erased and reprogrammed—a feature which ...
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... INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE20V8H-7 AND PALCE20V8H > ESD Protection and Clamping Device Rev Letter PALCE20V8H-7 A PALCE20V8H Programming Programming Pins only Voltage Detection Typical Input > Provides ESD Protection and Clamping Preload Circuitry Typical Output PALCE20V8 Family ...
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... ESD Protection V CC Preload Circuitry Device Rev Letter PALCE20V8H-10 M PALCE20V8H- PALCE20V8H-15 M PALCE20V8H--25 M PALCE20V8H- Input V CC 100 k Feedback Input I/O Topside Marking: Lattice/Vantis CMOS PLDs are marked on top of the package in the following manner: PALCEXXX Datecode (3 numbers) Lot ID (4 characters)––(Rev Letter) The Lot ID and Rev Letter are separated by two spaces ...
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POWER-UP RESET The PALCE20V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility ...
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TYPICAL THERMAL CHARACTERISTICS Measured ambient. These parameters are not tested. Parameter Symbol Parameter Description Thermal impedance, junction to case jc Thermal impedance, junction to ambient j a Thermal impedance, junction to ambient with air fl ...
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CONNECTION DIAGRAMS Top View SKINNYDIP CLK ...
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... PALCE20V8H-5 PALCE20V8H-7 PALCE20V8H-10 PALCE20V8H-15 PALCE20V8Q-15 PALCE20V8Q-20 PALCE20V8H-25 PALCE20V8Q-25 Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice/Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations ...