adau1361 Analog Devices, Inc., adau1361 Datasheet
adau1361
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adau1361 Summary of contents
Page 1
... Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL GENERAL DESCRIPTION The ADAU1361 is a low power, stereo audio codec supporting stereo 48 kHz record and playback from a 1.8 V analog supply. The stereo audio ADCs and DACs support sampling rates from 8 kHz to 96 kHz and a digital volume control. The ADAU1361 is ideal for battery-powered audio and telephony applications ...
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... ADAU1361 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Analog Performance Specifications ........................................... 3 Power Supply Specifications........................................................ 6 Typical Current Consumption .................................................... 6 Typical Power Management Measurements ............................. 7 Digital Filters ................................................................................. 8 Digital Input/Output Specifications........................................... 8 Digital Timing Specifications ..................................................... 9 Digital Timing Diagrams........................................................... 10 Absolute Maximum Ratings .......................................................... 12 Thermal Resistance .................................................................... 12 ESD Caution ...
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... AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3 capacitor = 20 μF 100 mV p-p @ 217 Hz 100 mV p kHz Scales linearly with AVDD AVDD = 1.8 V Rev Page ADAU1361 mode), input sample rate = 48 kHz, measurement S (digital output mA LOAD IH Min Typ Max 24 0.375 95 ...
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... ADAU1361 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Volume Control Step Volume Control Range PGA Boost Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation ...
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... P = output power per channel O − 4 dBFS AVDD = 1 6 AVDD = 3 21 AVDD = 1 3 AVDD = 3 10 capacitor = 20 μF 100 mV p-p @ 217 Hz 100 mV p kHz Rev Page ADAU1361 Min Typ Max 1.17 2.14 5 1.62 2. 0.375 95 AVDD/ 3.3 0.5 5 (1.56) 1 ...
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... ADAU1361 Parameter Interchannel Isolation REFERENCE Co mmon-Mode Reference Output POWER SUPPLY SPECIFICATIONS Table 2. Pa rameter SUPPLIES Voltage Digital I/O Current (IOVDD = 1.8 V) Slave Mode Master Mode Digital I/O Current (IOVDD = 3.3 V) Slave Mode Master Mode An alog Current (AVDD ) TYPICAL CU RRENT CONSUMPTION M ter clock = 12.288 MHz, input sample ...
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... ADAU1361 nditions e p ower Line Ou tput (dB ) ...
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... ADAU1361 DIGITAL FILTERS Table 5. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DIGITAL INPUT/OUTPUT SPECIFICATION −40°C < T < +85°C, IOVDD = 3.3 V ± 10%. ...
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... Digital microphone clock fall time Digital microphone clock rise time Digital microphone delay time for valid data Digital microphone delay time for data three-stated. Rev Page ADAU1361 f mode . S f mode . S , 768 × f mode . S f mode. ...
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... ADAU1361 DIGITAL TIMING DIAGRAMS t BIH BCLK t BIL t LIS LRCLK t SIS DAC_SDATA LEFT-JUSTIFIED MSB MODE t SIH DAC_S DATA MODE DAC_SDATA R IGHT-JUSTIFIED MODE 8- BIT CLOCKS (2 4-B IT DATA) 12- T CLOCKS BI (2 0-B IT DATA) 14- BIT CL (1 8-BIT 16- BIT CLOCKS (1 6-BI T DATA) t BIH BCLK t BIL LRCLK ...
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... CDH Figure 4. SPI Port Timing SCR SCLH SCS SCLL SCF 2 Figure Port Timing t t DCF DCR t t DDV DDH t t DDH DDV DATA2 DATA1 DATA2 Figure 6. Digital Microphone Timing Rev Page ADAU1361 t CLH t CLPH t COD t SCH t BFT ...
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... ADAU1361 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Power Supply (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range Storage Temperature Range Stresses above those listed under Absolute Maximum Ratin m ay cause permanent damage to the device. This is a stress r ating only ...
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... LOUTP AVDD 8 17 LOUTN NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO HE ADAU1361 GROUNDS. FOR INCREASED RELIABILIT SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 7. Pin Configuration 1 Description Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD, which also sets the highest input voltage that should be seen on the digital input pins ...
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... CCLK: SPI Clock. This pin can run continuously or be gated off between SPI transaction Exposed Pad. The exposed pad is connected internally to the ADAU1361 grounds. For increased reliability of the solder joints and maximum th mended that the pad be sold ered to the ground plane ...
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... DIGITAL 1kHz INPUT SIGNAL (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –60 –50 –40 –30 –20 DIGITAL 1kHz INPUT SIGNAL (dBFS) 0.04 0. 0.05 0.10 0.15 0.20 0.25 0.30 FREQUENCY (NORMALIZED TO Normalized ADAU1361 –10 0 –10 0 0.35 0. ...
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... ADAU1361 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 14. ADC Decimation Filter, 128× Oversampling, Normalized −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 15. ADC Decimation Filter, Double-Rate Mode, Normalized − ...
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... S Figure 22. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling, S 0.20 0.15 0.10 0.05 −0.05 −0.10 −0.15 −0.20 0.7 0.8 0.9 1 Figure 23. DAC Interpolation Filter Pass-Band Ripple, Double-Rate Mode, S Rev Page 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 f FREQUENCY (NORMALIZED Normalized 0.05 0.10 0.15 0.20 0.25 0.30 f FREQUENCY (NORMALIZED Normalized ADAU1361 0.45 0.50 0.35 0.40 ...
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... AUX RIGHT 1kΩ CLOCK SOURCE FROM VOLTAGE REGULATOR (1.8V TO 3.3V) 10µF 10µ 0.1µF 0.1µF DVDDOUT IOVDD LINP LINN ADAU1361 MICBIAS 0.1µF RINN RINP JACKDET/MICIN 10µF LAUX 10µF RAUX 49.9kΩ MCLK Figure 24. System Block Diagram Rev Page 10µF + 0.1µF 0.1µF 1 ...
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... DVDDOUT IOVDD AVDD AVDD MICBIAS LINN LINP ADAU1361 RINN RINP ADC_SDATA JACKDET/MICIN DAC_SDATA LAUX ADDR1/CDATA RAUX ADDR0/CLATCH MCLK Rev Page ADAU1361 10µF + 0.1µF 0.1µF 1.2nH 9.1pF LOUTP EARPIECE SPEAKER LOUTN RHP CAPLESS HEADPHONE MONOOUT OUTPUT LHP ROUTP EARPIECE SPEAKER ...
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... DVDDOUT IOVDD AVDD AVDD MICBIAS RHP MONOOUT LHP LINP LINN RINN RINP LOUTP ADAU1361 LOUTN ROUTP ROUTN JACKDET/MICIN ADC_SDATA DAC_SDATA LAUX LRCLK BCLK RAUX ADDR1/CDATA SDA/COUT SCL/CCLK MCLK ADDR0/CLATCH CM Rev Page 10µF + 9.1pF ...
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... The ADAU1361 can generate its internal clocks from a wide range of input clocks by using the on-board fractional PLL. The PLL accepts inputs from 8 MHz to 27 MHz. The ADAU1361 is provided in a small, 32-lead × LFCSP with an exposed bottom pad. Rev Page ...
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... PLL has locked. After lock is acquired, the ADAU1361 2.96 ms can be started by asserting the core clock enable bit (COREN) 2 Register R0 (clock control register, Address 0x4000). This bit 2.4 ms enables the core clock to all the internal blocks of the ADAU1361. Rev Page current draw of this , 512 × 768 × the base sampling rate ...
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... Poll the lock bit. 5. Assert the core clock enable after the PLL lock is acquired. The PLL control register (Register R1, Address 0x4002 48-bit register where all bits must be written with a single continuous write to the control p Rev Page ADAU1361 dure must be followed: ort. ...
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... ADAU1361 CLOCKING AND SAMPLING RATES R1: PLL CONTROL REGISTER MCLK ÷ X × N/M) CORE CLOCK Clocks for the converters and serial ports are derived from the core clock. The core clock can be derived directly from MCLK or it can be generated by the PLL. The CLKSRC bit (Bit 3 in Register R0, Address 0x4000) determines the clock source ...
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... S nal PLL: 16-bit binary number PLL: 16-bit binary number nly values are valid fault) 8 Rev Page ADAU1361 = 48 kHz, then S fractional PLL parameter settings for 44.1 kHz and n the range of 41 MHz to 54 MHz, to account when calculating PLL ...
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... ADAU1361 Table 16. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider ( 14.4 2 19.2 2 19. Table 17. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider ( 14.4 2 19.2 2 19. Table 18. Integer PLL Parameter Set ...
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... RDVOL[5:0] ALC CONTROL INPUT SIGNAL PATHS The ADAU1361 can accept both line level and microphone inputs. The analog inputs can be configured in a single-ended or differential configuration. There is also an input for a digital microphone. Each of the six analog inputs has individual gain controls (boost or cut) ...
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... When using a digital microphone connected to the JACKDET/ MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008) must be set to enable the microphone input and disable the jack detection function. The ADAU1361 must operate in master mode and source BCLK to the input clock of the digital microphones. ADAU1361 The digital microphone signal bypasses record path mixers and ADCs and is routed directly into the decimation filters ...
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... ANALOG- TO-DIGITAL CONVERTERS The ADAU1361 uses two 24-bit Σ-Δ analog-to-digital converters (ADCs) with selectable oversampling rates of 64× or 128× (selected by Bit 3 in Register R17, Address 0x4017). ADC Full-Scale Level The full-scale input to the ADCs (0 dBFS) depends on AVDD ...
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... ADAU1361 AUTOMATIC L EVEL CONTROL (ALC) The ADAU1361 contains a hardware automatic level control (ALC). The ALC is designed to continuously adjust the PGA gain to keep the recording volume constant as the input level varies. For optimal noise performance, the ALC uses the analog PGA to adjust the gain instead of using a digital method. This ensures that the ADC noise is not amplified at low signal levels ...
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... This causes an unpleasant sound. To reduce this effect, the noise gate in the ADAU1361 uses a combination of a timeout period and hysteresis. The timeout period is set to 250 ms, so the signal must consistently be below the threshold for 250 ms before the noise gate operates ...
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... NGTYP[1:0] bits to 10. In this mode, the ADAU1361 improves the sound of the noise gate operation by first fading the PGA gain over a period of about 100 ms to the minimum PGA gain value. The ADAU1361 does not do a hard mute after the fade is complete, so some small background noise will still exist. THRESHOLD ...
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... TO +6dB LEFT DAC RIGHT DAC OUTPUT SIGNAL PATHS The outputs of the ADAU1361 can be configured as a variety of differential or single-ended outputs. All analog output pins are capable of driving headphone or earpiece speakers. There are selectable output paths for stereo signals or a downmixed mono output. The line outputs can drive a load of at least 10 kΩ ...
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... ADAU1361 Capless Headphone Configuration The headphone outputs can be co nfigur configuration with the MONOOUT pin used virtual ground reference. Figure 43 depicts a typical playback path in a capless headphone configuration. Table 19 lists the register settings for this configuration. As shown in this table, the ...
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... Address 0x4020) and Register R27 (playback L/R mixer right (M ixer 6) line output control register, Address 0x4021). MIXER 3 LEFT DAC utput e speakers of MIXER 4 RIGHT DAC ed mode, Figure 46. Differential Line Output Configuration he signals, and Rev Page ADAU1361 l regist , MX5G3[1:0] LOUTVOL[5:0] MIXER 5 LOUTP –1 LO UTN –1 ROUTN MX6G4[1:0] ROUTVOL[5:0] ...
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... ADAU1361 and the system mode, the ADAU1361 is always a slave on the bus, meaning that it cannot initiate a data transfer. Each slave device is recognized by a unique address. The address and R/ W byte format is shown in Table 21. The address resides in the first ...
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... SDA (CONTINUED) FRAME 5 READ DATA BYTE 1 location is reached while in write mode, the data for the invalid 1361 byte is not loaded into any subaddress register acknowledge ster is issued by the ADAU1361, and the part returns to the idle condi on. ess ADDR1 ...
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... Chip address, AS Subaddress R high set to 1 (read). This causes the ADAU1361 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU13 Figure gure shows an example of a read from sequential single-byte registers ...
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... The CCLK signal latches CDATA on a low-to-high transition. COUT data is shifted out of the ADAU1361 on the falling edge of CCLK and shou clocked into a receiving device, such as a microcontroller, on the CCLK rising edge. The CDATA signal carries the serial input data, and the COUT signal is the serial output data ...
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... BCLK transitions in each LRCLK frame. The LRCLK in TDM mode can be input to the ADAU1361 either as a 50% duty cycle clock bit-wide pulse. In TDM kHz. Table 24 lists the modes in which the serial output port can function ...
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... LRCLK BCLK MSB MSB – 1 MSB – 2 SDATA Figu re 58. TDM 8 Mode S LOT 2 SLOT 3 SLOT Figure 59. TDM 8 M ode with Pulse Word C lock Rev Page ADAU1361 RIGHT CHANNEL MSB LSB SLOT 6 SLOT 7 MSB SLO T 6 SLOT 7 ...
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... Components in an analog sig from digital signals. EXPOSED PAD PCB DESIGN The ADAU1361 has an exposed pad on the underside of the LFCSP. This pad is used to couple the package to the PCB for heat dissipation when using the outputs to drive earpiece or headphone loads. When designing a board for the ADAU1361, ...
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... Rese rved PO MODE P HPBIAS[1:0] DACBIAS[1:0] DACMONO[1:0] DACPOL Reserved LDAVOL[7:0] RDAVOL[7:0] ADCSDP[1:0] DACSDP[1:0] CDATP[1:0] CLCHP[1:0] Reserved Reserved JDSTR Reserved Rev Page ADAU1361 Bit 3 Bit 2 Bit 1 Bit 0 CLKSRC INFREQ[1:0] COREN X[1:0] Type Lock PLLEN JDMUTE Reserved JDPOL RBIAS[1:0] Reserved LINNG[2:0] MX1EN MX1AUXG[2:0] RINNG[2:0] ...
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... ADAU1361 CONTROL REGISTER DETAIL S All registers except for the PLL con trol register are one-byte write and read registers. R0: Clock Control 1638 4 (0x4000) Bit 7 Bit 6 Bit 5 Reserved Table 27. Clock Control Register Bit Bit Name Description 3 CLKSRC Clock source select dire ct from MCLK pin (default). ...
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... Pin F unc tion Jack detect off (d efault) Jack detect on Digit al microphone input Reserved t). olarity. Detects high gnal. (default). . Rev Page Bit 2 Bit 1 Reserved jack detect function or c onfigures the pin for a digital ADAU1361 Bit 0 JDPOL et to 01. ...
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... ADAU1361 R3: Record Power Managem ent 16393 (0x40 Th is regis ter ma nag es the p ower co nsumption for the re r ecord pa mixers, th and PG As can b e set erforma e mode, and extreme po nc wer sa m ode offers the high t performanc es e with Bit 7 Bit 6 ...
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... Bit 3 egiste r Gain Mute (default) −12 dB −9 dB −6 dB − ain Mute (default) −12 dB −9 dB −6 dB − enable in the r ecord path. Referred to as Rev Page ADAU1361 Bit 2 Bit 1 Bit 0 LINNG[2:0] MX1EN Mixer 1. 1. ...
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... ADAU1361 R5: Record Mixer Left (Mixer 1) Control 1 16395 (0x400B) This register controls the boost gain of the left channel differential PGA input and the gain for the left channel auxiliary input in the record path. The left ch annel recor d mixe Bit 7 Bit Reserved Table 32 ...
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... RINP pin, input to Mixer 2. Gain Mute (de fault) −12 dB −9 dB −6 dB − nded input from the RINN pin, input to Mixer 2. Gain Mute (default) −12 dB −9 dB −6 dB − Rev Page ADAU1361 Bit 2 Bit 1 Bit 0 RINNG[2:0] MX2E ...
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... ADAU1361 R7: Record Mixer Right (Mixer 2) Control 1 16397 (0x400D) This register controls the boost gain of the right channel differential PGA input and the gain for the right channel auxiliary input in the record path. The right c hannel reco rd mi Bit 7 Bit Reserved Table 34 ...
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... Bit 4 Bit 3 MPERF s is enabled for high performance or normal operation. High performance operation sources tion of AV DD. Rev Page ADAU1361 Bit 2 Bit 1 Bit 0 RDMU TE RDEN Bit 2 Bit 1 Bit 0 MBI Reserved MBIEN plete ...
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... ADAU1361 R11: ALC Control 0 16401 (0x4011) Bit 7 Bit 6 Bit 5 PGASLEW[1:0 ] Table 38. ALC Control 0 Register Bit Bit Name Description [7:6] PGASLEW[1:0] PGA volume slew time when the ALC is off. The slew time is the period of time that a volume increase or decrease takes to ramp and Register R9 (right differential input volume control). ...
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... ALC Target −28.5 dB (default) −27 dB −25.5 dB −24 dB −22 −21 dB −19.5 dB −18 dB −16.5 dB −15 dB −13.5 dB −12 dB −10.5 dB −9 dB −7.5 dB −6 dB Rev Page ADAU1361 Bit 1 Bit 0 ALCTARG[3:0] ut ...
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... ADAU1361 R13: ALC Control 2 16403 (0x4013) Bit 7 Bit 6 Bit 5 ALCATCK[3:0] Table 40. ALC Control 2 Register Bit Bit Name Description [7:4] ALCATCK[3:0] ALC attack time. The attack time sets how fast the ALC starts attenuating after an increase in input level above the target. A typical setting for music recording is 384 ms, and a typical setting for voice recording is 24 ms. ...
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... This can be set for the falling or rising edge ge that trig gers the beginning of the left channel audio frame. This can be set e LRCLK. Channels per LRCLK Frame Stereo (default) TDM 4 TDM 8 Reserved Rev Page ADAU1361 Bit 1 Bit 0 4:0] Bit 1 Bit 0 CHPF[1:0] MS ...
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... ADAU1361 Bit Bit Name Description 0 MS Serial da ta por serial por t slave 0 = slave mod default maste r mode. R16: Ser ial Port Con trol 1 16406 (0x4016) Bit 7 Bit 6 Bit 5 BPF[2:0] Table 43. Serial Port Control 1 Register Bit Bit Name Description [7:5] BPF[2:0] Num ber of bit clock cycles per L ...
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... Sampling Rate /1 /0.5 S Reserved Rev Page ADAU1361 Bit 2 Bit 1 Bit 0 CONVSR[2:0] Sampling Rate ( kHz kHz, base (default) 8 kHz 12 kHz 16 kHz 24 kHz 32 kHz 96 kHz ...
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... ADAU1361 R18: Converter Control 1 16408 (0x4018) Bit 7 Bit 6 Bit 5 Reserved Table 45. Converter Control 1 Register Bit Bit Name Description [5:4] DAMUTE[1:0] DAC mute. Setting [3:2] ADMUTE[1:0] ADC mute. Setting [1:0] ADPAIR[1:0] On-chip ADC serial data selection in TDM 4 or TDM 8 mode. Setting ...
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... ADC or the right digital ut. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 72 for a of the volume settings. Vo lume At tenuatio (default) −0.375 dB −0.75 dB … −95.25 dB −95.625 dB Rev Page ADAU1361 Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 ...
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... ADAU1361 R22: Playback Mixer Left (Mixer 3) Control 0 164 Bit 7 Bit 6 Bit 5 Reserved MX3RM MX3LM Table 49. Playback Mixer Left (Mixer 3) Control 0 Register Bit Bit Name Description 6 MX3RM Mixer input mute. Mutes the right DAC input to the left channel playback mixer (Mixer 3). ...
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... Gain Mute (default) −15 dB −12 dB −9 dB −6 dB − Rev Page ADAU1361 Bit 1 Bit 0 MX3G1[3:0] converters and gain ...
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... ADAU1361 R24: Playback Mixer Right (Mixer 4) Control 0 16414 (0x401E) Bit 7 Bit 6 Bit 5 Reserved MX4RM MX4L Table 51. Playback Mixer Right (Mixer 4) Control 0 Register Bit Bit Name Description 6 MX4RM Mixer input mute. Mutes the right DAC input to the right channel playback mixer (Mixer 4). ...
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... Gain Mute (default) −15 dB −12 dB −9 dB −6 dB − Rev Page ADAU1361 Bit 2 Bit 1 Bit 0 MX4G1[3:0] nverters and gain ...
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... ADAU1361 R26: Playback L/R Mixer Left (Mixer 5) Line Output Control 164 Bit 7 Bit 6 Bit 5 Reserv ed Table 53. Playback L/R Mixer Left (Mixer 5) Line Output Control Register Bit Bit Name Description [4:3] MX5G4[1:0] Mixer input gain boost. The signal from the right channel playback mixer (Mixer 4) can be boosted in the L/R left playback mixer (Mixer 5) ...
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... Bit 3 Gain Boost Common-mode output (default Reserved Bit 4 Bit 3 LHPVOL[5:0] e Control Register Volume −57 dB (default) … … phone volume f or dual channel control. Rev Page ADAU1361 Bit 2 Bit 1 Bit 0 MX7EN MX7[1:0] Bit 2 Bit 1 Bit 0 LHPM HPDUAL ...
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... ADAU1361 R30: Playback Headphone Right Volume Control 16420 (0x4024) Bit 7 Bit 6 Bit 5 Table 57. Playback Headphone Right Volume Control Register Bit Bit Name Description [7:2] RHPVOL[5:0] Headphone volume control for right channel, RHP output. Each 1-bit step corresponds increase in volume. See Table 73 for a complete list of the volume settings. ...
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... Register , volume c ontrol is disabled. See Table 73 for a complete list of the volume settings. Volume −57 dB (default) … … uld be set to 1 (headphone output). Rev Page ADAU1361 Bit 2 Bit 1 Bit 0 ROUTM ROMODE e settings. ts (active low). Bit 2 Bit 1 Bit 0 MONOM MOMODE n volume ...
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... ADAU1361 R34: Playback Pop/Click Suppression 16424 (0x4028) Bit 7 Bit 6 Bit 5 Reserved Table 61. Playback Pop/Click Suppression Register Bit Bit Name Description 4 POPMODE Pop suppression circuit power-save mode. The pop suppression circuits charge faster in normal operation; however, after they are charged, they can be put into low power operation. ...
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... Bit 4 Bit 3 LDAVOL[7:0] olume attenua tion for left channe l inputs from the left DAC. Each bit corresponds lume Attenuation 0 dB (default) −0.375 dB −0.75 dB … −95.25 dB −95.625 dB Rev Page ADAU1361 Bit 2 Bit 1 Bit 0 DEMPH DACEN [1:0] Bit 2 Bit 1 Bit 0 ...
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... ADAU1361 R38: DAC Control 2 16428 (0x402C) Bit 7 Bit 6 Bit 5 Table 65. DAC Control 2 Register Bit B it Name D escription [7:0] R DAVOL[7:0] Co ntrols the digital volume attenuation for right channel inputs from the right DAC. Each bit corresponds 0. 375 dB step with slewing between settings ...
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... UT pin are approximately 2.0 mA and 4.0 mA, respectively. ately 0.8 mA and 1.7 mA, respectively. The high drive strength mode eded. Bit 4 Bit 3 Res erved ive strength. Rev Page ll-up/ pull-down resisto rs set the co Bit 2 Bit 1 SCLP[1:0] SDAP[1:0] Bit 2 Bit 1 ADAU1361 ntrol port Bit 0 Bit 0 SDASTR ...
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... ADAU1361 R42: Jack Detect Pin Control 16433 (0x4031) Bit 7 Bit 6 Bit 5 Reserved JDSTR Table 69. Jack Detect Pin Control Register Bit Bit Name Description 5 JDSTR JACKDET/MICIN drive strength low (default high. [3:2] JD P[1:0] JAC KDET/MICIN pad pull-up/pu Setting Bit 4 Bit 3 Bit 2 Reserved ...
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... Rev Page ADAU1361 Volu me Se tting (dB) 26.25 27 27.75 28.5 29.25 30 30.75 31.5 32.25 33 33.75 34.5 35.25 Noise Gate Threshold (dB) −76.5 −75 −73.5 −72 −70.5 −69 − ...
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... ADAU1361 Table 72. R20, R21, R37, and R38 Volu Binary Value Volume Attenuation ( 00000000 0 00000001 −0.375 00000010 −0.75 00000011 −1.125 00000100 −1.5 00000101 −1.875 00000110 −2.25 00000111 −2.6 25 00001000 −3 00001001 −3.37 5 00001010 −3.75 00001011 −4.1 25 00001100 −4.5 00001101 − ...
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... Rev Page ADAU1361 Volume Attenuation (dB) −54.375 −54.75 −55.125 −55.5 −55.875 −56.25 −56.625 −57 −57.375 −57.75 −58.125 −58.5 −58.875 −59.25 − ...
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... ADAU1361 Binary Value Volume Attenuation (dB) 11000010 −72.75 11000011 −73.125 11000100 −73.5 11000101 −73.875 11000110 −74.25 11000111 −74.625 11001000 −75 11001001 −75.375 11001010 −75.75 11001011 −76.125 11001100 −76.5 11001101 −76.875 11001110 −77.25 11001111 −77.625 11010000 − ...
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... Rev Page ADAU1361 ...
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... MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model T mper e ature Range 1 ADAU1361BCPZ −40°C to +85°C 1 ADAU1361BCPZ-R7 −40°C to +85°C 1 ADAU1361BCPZ-RL −40°C to +85°C 1 EVAL-ADAU1361Z RoHS Compliant Part. 5.00 BSC SQ 0.60 MAX 24 0.50 BSC TOP 4.75 VIEW BSC SQ 0.50 0.40 17 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM ...
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... NOTES Rev Page ADAU1361 ...
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... ADAU1361 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07679-0-1/09(0) Rev Page ...