adau1442 Analog Devices, Inc., adau1442 Datasheet
adau1442
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adau1442 Summary of contents
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... Supports serial and TDM I/ 192 kHz S Multichannel byte-addressable TDM serial port Pool of 170 ms digital audio delay (at 48 kHz) Clock oscillator for generating master clock from crystal PLL for generating core clock from common audio clocks ADAU1442/ ADAU1445/ ADAU1446 1.8 REGULATOR SPDIFI SDATA_IN[8:0] ...
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Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 3 Specifications ..................................................................................... 4 Digital Timing Specifications ..................................................... 6 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions........................... ...
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... ASRC outputs. This routing scheme, which can be modified at any time via control registers, allows for maximum system flexibility. The ADAU1442, ADAU1445, and ADAU1446 differ only in ASRC functionality and packaging. The ADAU1442 and ADAU1445 con tain 16 channels of ASRCs and are packaged in a TQFP, whereas the ADAU1446 contains no ASRCs and is packaged in an LQFP ...
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... Analog Voltage (AVDD) Digital Voltage (DVDD) PLL Voltage (PVDD) IOVDD Voltage (IOVDD) Supply Current Analog Current (AVDD) PLL Current (PVDD) Digital Current (DVDD) of ADAU1442, ADAU1445 Digital Current (DVDD) of ADAU1446 I/O Current (IOVDD) Analog Current, Reset Digital Current, Reset = 25°C, master clock input = 12.288 MHz, ...
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... Parameter PLL Current, Reset Power Dissipation AVDD, DVDD, PVDD During Operation of ADAU1442, ADAU1445 AVDD, DVDD, PVDD During Operation of ADAU1446 Reset, All Supplies TEMPERATURE RANGE Functionality Guaranteed ASYNCHRONOUS SAMPLE RATE CONVERTERS Dynamic Range I/O Sample Rate I/O Sample Rate Ratio THD + N PLL Operating Range ...
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DIGITAL TIMING SPECIFICATIONS Table 2. 1 Parameter t MIN MASTER CLOCK t TBD MP SERIAL PORT f TBD BCLK t 40, TBD BIL t 40, TBD BIH t 10, TBD LIS t 10, TBD LIH t 10, TBD SIS t ...
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Digital Timing Diagrams t BIH BCLKx INPUT t BIL t LIS LRCLKx INPUT t SIS SDATA_INx LEFT-JUSTIFIED MSB MODE t SIH SDATA_INx MODE SDATA_INx RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT ...
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CLS t CLATCH CCPH CCLK CDATA t CDS COUT t SCH SDA t SCL t MP MCLK RESET t CCPL t CDH Figure 4. SPI Port Timing SCR SCLH SCS SCLL SCF 2 ...
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Table 3. Rating Parameter DVDD to GND 2.2 V AVDD to GND 4.0 V IOVDD to GND 4.0 V DGND – 0 IOVDD + 0.3 V Digital Inputs Maximum ...
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... ADAU1442/ADAU1445/ADAU1446 TOP VIEW (Not to Scale) Figure 7. Pin Configuration Description Digital Ground. The AGND, DGND, and PGND pins should be tied directly together in a common ground plane. DGND pins should be decoupled to a DVDD pin with a 100 nF capacitor. Input and Output Supply. The voltage on this pin sets the highest input voltage that should be present on the digital input pins ...
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Pin No. Mnemonic Type 1 6 BCLK2 D_IO 7 LRCLK2 D_IO 8 SDATA_IN1 D_IN 9 BCLK1 D_IO 10 LRCLK1 D_IO 11 SDATA_IN0 D_IN 12 BCLK0 D_IO 15 LRCLK0 D_IO 16 MP11 D_IO 17 MP10 D_IO 18 MP9 D_IO 19 MP8 ...
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Pin No. Mnemonic Type 1 30 CLKMODE0 D_IN 31 RSVD D_IN 32 PLL2 D_IN 33 MP7 D_IO 34 MP6 D_IO 35 MP5 D_IO 36 MP4 D_IO 40 VDRIVE A_OUT 41 XTALO A_OUT 42 XTALI A_IN 43 PLL_FILT A_OUT 44 PVDD ...
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Pin No. Mnemonic Type 1 64 BCLK11 D_IO 65 LRCLK11 D_IO 66 SDATA_OUT7 D_OUT 67 BCLK10 D_IO 68 LRCLK10 D_IO 69 SDATA_OUT6 D_OUT 70 BCLK9 D_IO 71 LRCLK9 D_IO 72 SDATA_OUT5 D_OUT 73 SDATA_IN8 D_IN 74 BCLK8 D_IO 78 LRCLK8 ...
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Pin No. Mnemonic Type 1 93 LRCLK5 D_IO 94 SDATA_OUT1 D_OUT 95 SDATA_IN4 D_IN 96 BCLK4 D_IO 97 LRCLK4 D_IO 98 SDATA_OUT0 D_OUT 99 SDATA_IN3 D_IN 1 PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = ...
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... SYSTEM BLOCK DIAGRAM +3.3V VDRIVE ADAU1442/ ADAU1445/ ADAU1446 1.8V REGULATOR S/PDIF SPDIFI RECEIVER SDATA_IN[8:0] SERIAL DATA 9 INPUT PORT (24-CHANNEL (×9) DIGITAL AUDIO INPUT † BIT CLOCK (BCLK † FRAME CLOCK (LRCLK) 6 DVDD 2 *SPI THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS. ...
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... Within the ADAU144x family, there are three devices, each distinguished by the number of on-board ASRCs and maximum sample rates. The ADAU1442 contains eight 2-channel ASRCs, the ADAU1445 contains two 8-channel ASRCs, and the ADAU1446 has no ASRCs. Two sets of serial ports at the input and output can operate in a ...
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... The ADAU144x is fabricated on a single monolithic integrated circuit and is housed in a 100-lead package for operation over the −40°C to +105°C temperature range. The ADAU1442 and ADAU1445 are housed in a 100-lead TQFP package, with an exposed pad to assist in heat dissipation. The ADAU1446, due to its lower power consumption, is housed in a 100-lead LQFP package ...
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INITIALIZATION Power-Up Sequence The ADAU144x has a built-in initialization period, which allows for sufficient time for the PLL to lock and the registers to initialize their values positive edge of RESET , the PLL settings are immediately set ...
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MASTER CLOCK AND PLL Using the Oscillator The ADAU144x can use an on-board oscillator to generate its master clock. However, an external crystal must be attached to complete the oscillator circuit. The on-board oscillator is designed to work with a ...
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Table 7. PLL Modes Input to MCLK DSP Core Rate 1 (XTALI Pin) Normal 64 × f S,NORMAL 128 × f S,NORMAL 256 × f S,NORMAL 384 × f S,NORMAL 512 × f S,NORMAL Double 32 × f S,DUAL 64 ...
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PLL Loop Filter The PLL loop filter should be connected to the PLL_FILT pin. This filter, shown in Figure 11, includes three passive components— two capacitors and a resistor. The values of these components do not need to be exact; ...
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Table 10. Bit Descriptions of Register 0xE220 Bit Position Description [15:5] Reserved [4:0] Start pulse select 00000 = internally generated normal rate (f 00001 = internally generated double rate (f 00010 = internally generated quad rate (f 00011 = f ...
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... Second, the collector of the transistor must be able to dissipate the heat generated when regulating from 3 1.8 V. The maximum digital current draw of the ADAU1442 and ADAU1445, which use ASRCs, is 445 (TBD) mA. The equation to determine the transistor’s minimum power dissipation specifications is as follows: (3.3 V − ...
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CONTROL PORT Overview The ADAU144x can operate in one of three control modes: I control mode, SPI control mode, or self-boot mode (no external controller). The ADAU144x has both a 4-wire SPI control port and a 2-wire ...
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A Logic 0 on the LSB of the first byte means the master writes information to the peripheral. A Logic 1 on the LSB of the first byte means the master reads information from the peripheral. A data transfer ...
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SCL SDA START BY MASTER FRAME 1 CHIP ADDRESS BYTE SCL (CONTINUED) SDA (CONTINUED) FRAME 3 SUBADDRESS BYTE 2 SCL (CONTINUED) SDA (CONTINUED) FRAME 5 READ DATA BYTE 1 CHIP ADDRESS, SUBADDRESS R/W ...
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SPI Port 2 By default, the ADAU144x mode, but it can be put into SPI control mode by pulling CLATCH low three times. The SPI port uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA, and ...
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Self-Boot On power-up, the ADAU144x can load a program and a set of parameters that are saved in an external EEPROM. Combined with the auxiliary ADC and the multipurpose pins, this can potentially eliminate the need for a microcontroller in ...
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SERIAL DATA INPUT/OUTPUT The flexible serial data input and output ports of the ADAU144x can be set to accept or transmit data in a 2-channel (usually I format), packed TDM4, or standard 4-, 8-, or 16-channel TDM stream. Data is ...
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Table 17. Configurations for Standard Audio Data Formats Format LRCLK Polarity Frame begins on (Figure 22) falling edge Left-Justified Frame begins on (Figure 23) rising edge Right-Justified Frame begins on (Figure 24) rising edge TDM with Clock ...
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Serial Audio Data Timing Diagrams Figure 22 to Figure 26 show timing diagrams for standard audio data formats. LRCLKx BCLKx SDATA_INx, MSB SDATA_OUTx LRCLKx LEFT CHANNEL BCLKx SDATA_INx, MSB SDATA_OUTx LRCLKx BCLKx SDATA_INx, MSB SDATA_OUTx LRCLKx BCLKx SDATA_INx, SDATA_OUTx LRCLKx ...
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... The ADAU1445, which contains two 8-channel ASRCs, and the ADAU1446, which contains no ASRCs, do not require as many clock domains as the ADAU1442. However, all clock domain pins are available on every IC in the ADAU144x family system with no sample rate conversion and with serial ports in ...
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Serial Clock Modes and Settings Dejitter Window Register (Address 0xE221) Table 19. Bit Descriptions of Register 0xE221 Bit Position Description [15:6] Reserved [5:0] Dejitter window 000000 = dejitter circuit bypass 000001 = minimum window … 111111 = maximum window Register ...
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Packed TDM4 Mode A special TDM mode is available that allows four channels to be fit into a space of 64 bit clock cycles. This mode is called packed TM TDM4 mode, or MOST mode. MOST (Media Oriented Systems Transport) ...
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SERIAL INPUT PORTS The serial input ports convert standard I into 16-, 20-, and 24-bit audio signals for input to the audio processor. They support TDM2, TDM4, TDM8, and TDM16 time division multiplexing schemes and I justified, MSB delay-by-12 and ...
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SDATA_IN0 SDATA_IN1 SDATA_IN2 SERIAL SDATA_IN3 INPUT SDATA_IN4 PORTS SDATA_IN5 (×9) SDATA_IN6 SDATA_IN7 SDATA_IN8 CLOCK DOMAIN 18:2 SELECTOR (× 4:2 4:2 4:2 4 ...
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SERIAL INPUT PORT MODES AND SETTINGS Each of the nine serial input ports is controlled by setting an individual 2-byte word in the serial input mode register for each port (see Table 23 for the register addresses). Each serial data ...
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Bit Position Description [7:6] Word length bits bits bits 11 = flexible TDM mode [5:3] MSB position 2 000 = I S (delayed by 1) 001 = left justified (delayed by ...
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BCLK POLARITY LRCLKx BCLKx SDATA_INx LRCLKx BCLKx SDATA_INx LRCLK POLARITY LRCLKx LRCLKx Word Length Bits (Bits[7:6]) These bits set the word length of the input data to 16, 20 bits. If the input signal has more data bits ...
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In master mode, the clock domain selector is bypassed, and the assignments described in Table 26 are used. Table 26. Output Clock ...
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Serial Output Port Modes Registers (Address 0xE040 to Address 0xE049) Table 27. Addresses of Serial Output Port Modes Registers Address Decimal Hex Name 57408 E040 Serial Output Port 0 modes 57409 E041 Serial Output Port 1 modes 57410 E042 Serial ...
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Table 28. Bit Descriptions of Serial Output Port Modes Registers Bit Position Description [15] Clock output enable 0 = LRCLK and BCLK output pins disabled 1 = LRCLK and BCLK output pins enabled [14] Frame sync type 0 = LRCLK ...
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Clock Output Enable Bit (Bit 15) This bit controls the serial port’s respective bit clock as well as the left and right clocks. When this bit is set to 1, the clock pins are set to output. When this bit ...
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High Speed Slave Interface Mode Register (Address 0xE049) Table 29. Bit Descriptions of Register 0xE049 Bit Position Description [15:1] Reserved [0] High speed slave interface mode 0 = disabled 1 = enabled High Speed Slave Interface Mode Bit (Bit 0) ...
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FLEXIBLE AUDIO ROUTING MATRIX (FARM) The routing matrix distributes audio signals among the serial inputs, serial outputs, ASRCs, S/PDIF receiver and transmitter, and DSP core. This simplifies the design of complex systems that require many inputs and outputs with different ...
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Routing Matrix Functionality Serial Input Ports The far left side of Figure 36 represents the audio input pins to the ADAU144x, namely SDATA_IN0 to SDATA_IN8 and SPDIFI. The serial audio data signals can be represented in any standard mode, including ...
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Flexible Audio Routing Matrix—Input Side Up until this point in the audio signal flow, all signals can be asynchronous to each other. However, before entering the DSP for processing, the signals must be synchronized to the same clock. Therefore, on ...
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... ASRC pairs. This allows the ASRCs to be placed both before and after the DSP. Figure 43 and Figure 44 show examples of how the ASRCs can be used both before and after the DSP. ASYNCHRONOUS Figure 42. Synchronous and Asynchronous Zones of the ADAU1442 and ADAU1445 FROM DSP FROM S/PDIF Rx ...
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Sample Rate Conversion Before the DSP If asynchronous input signals are present in the system, they must be routed through the ASRC before being processed by the DSP. This is made possible by routing the asynchronous signals through the input ...
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Flexible Audio Routing Matrix—Output Side Much like the input side, the output side of the flexible audio routing matrix takes several stereo pairs, which can be asynchronous, and connects them to the 12 stereo pairs that will be output from ...
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OUTPUT CHANNELS (24 CH 10, 11 12, 13 14, 15 16, 17 18, 19 20, 21 22, 23 FLEXIBLE AUDIO ROUTING MATRIX MODES AND SETTINGS Table 30. Addresses of Flexible ...
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... The inputs to each of the eight ASRCs can come from any stereo pair from either the serial input channels or the DSP core. In the case of the ADAU1442, each stereo input to the ASRCs can receive a separate data input, and all of these sources may be asynchronous to one another. ...
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ASRC Input Data Selector Bits (Bits[5:0]) As shown in Figure 49, the gray box representing the input side of the flexible audio routing matrix can be thought multiplexer. Any input to the box can make a one-to-one ...
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... S,NORMAL S,DUAL In the case of the ADAU1442, each of the eight stereo ASRCs can have separate output rates. In the case of the ADAU1445, each stereo output from the ASRCs can have a separate data output; however, all outputs ...
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Serial Output Select Pairs[11:0] Registers (Address 0xE090 to Address 0xE09B) Table 33. Bit Descriptions of Serial Output Select Pairs[11:0] Registers Bit Position Description [15:6] Reserved [5:0] Serial output data selector 010000 = DSP Output Pair 0 (Channel 0, Channel 1) ...
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Serial Output Data Selector Bits (Bits[5:0]) These bits select where each of the 12 stereo serial output channels come from. The channels can either come from one of the 12 DSP core stereo outputs or from one of the eight ...
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... The sample rate converters operate completely independent of the serial ports and DSP core, connecting via the flexible audio routing matrix. The ADAU1442 has eight stereo sample rate converters. ASRC MODES AND SETTINGS Table 34. Addresses of ASRC Modes Registers ...
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In the case of the ADAU1446, setting these registers does not affect system operation in any way. ASRC[7:4] Mute Ramp Disable Register (Address 0xE143) Table 38. Bit Descriptions of Register 0xE143 Bit Position Description [15:1] Reserved [0] ASRC[7:4] (Channels[15:8]) mute ...
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DSP CORE The DSP core performs calculations on audio data as specified by the instruction codes stored in program RAM. Because SigmaStudio generates the instructions not necessary to have a detailed knowledge of the DSP core to use ...
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Numeric Formats DSP systems commonly use a standard numeric format. Fractional number systems are specified by an A.B format, where A is the number of bits to the left of the decimal point and B is the number of bits ...
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RELIABILITY FEATURES The ADAU144x contains several subsystems designed to increase the reliability of the system in which it is used. When these functions are used in conjunction with an external host controller device, the DSP can recover from serious errors, ...
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Watchdog Modes and Settings Watchdog Registers (Address 0xE210 to Address 0xE212) Table 42. Register Details of Watchdog Registers Address Decimal Hex Register 57872 E210 Watchdog enable 57873 E211 Watchdog Value 1 57874 E212 Watchdog Value 2 A program counter watchdog ...
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RAMS The ADAU144x has 4k words of program RAM, 4k words of parameter RAM, and 8k words of data RAM. Program RAM Table 45. Register Details of Program RAM Address Decimal Hex Name 8192 2000 Program RAM The program RAM ...
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S/PDIF RECEIVER AND TRANSMITTER The ADAU144x features a set of on-chip S/PDIF data ports, which can be wired directly to transmitters and receivers for easy interfacing to other S/PDIF-compatible equipment. S/PDIF Receiver The S/PDIF input port is designed to accept ...
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S/PDIF MODES AND SETTINGS Table 51. Addresses of S/PDIF Modes Registers Address Decimal Hex Name 57536 E0C0 S/PDIF receiver—read auxiliary output 57537 E0C1 S/PDIF transmitter— on/off switch 57538 E0C2 S/PDIF read channel status, Byte 0 57539 E0C3 S/PDIF read channel ...
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Auxiliary Outputs—Set Enable Mode Register (Address 0xE0C8) Table 56. Bit Descriptions of Register 0xE0C8 Bit Position Description [15:2] Reserved [1:0] Word length 00 = auxiliary outputs are always off auxiliary outputs are always on auxiliary outputs ...
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Enable S/PDIF Output Register (Address 0xE241) Table 61. Bit Descriptions of Register 0xE241 Bit Position Description [15:3] Reserved [2] Output mode TDM [1] Group 2 enable 0 = Group ...
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MULTIPURPOSE PINS The ADAU144x includes 12 multipurpose pins that can be used either as digital general-purpose inputs/outputs (GPIOs inputs to the 4-channel auxiliary ADC. Each of the 12 multipurpose pins is controlled by a 4-bit mode. Pins can ...
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... The sample and bit rates are too low to convert signals for audio applications. There are four single-channel ADCs in the ADAU1442/ ADAU1445/ADAU1446. The input can be filtered using several methods. The specific filtering modes can be set as described in Table 66 ...
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When interfacing the ADAU144x to other devices in the system, it may be necessary to set the drive strength of each pin. DRIVE STRENGTH MODES AND SETTINGS Bit Clock Pad Strength Register (Address 0xE247) This register controls the pad drive ...
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Frame Clock Pad Strength Register (Address 0xE248) This register controls the pad drive strength of all frame clock pins configured in master mode. The default 2 mA setting should be adequate for most applications. The 6 mA setting should be ...
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Multipurpose Pin Pad Strength Register (Address 0xE249) This register controls the pad drive strength of all multipurpose pins configured as outputs. The default 2 mA setting should be adequate for most applications. The 6 mA setting should be used only ...
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Serial Data Output Pad Strength Register (Address 0xE24A) This register controls the pad drive strength of all serial data output pins. The default 2 mA setting should be adequate for most applications. The 6 mA setting should be used only ...
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Other Pad Strength Register (Address 0xE24C) This register controls the pad drive strength of the communications port, S/PDIF output, and master clock outputs. The default 2 mA setting should be adequate for most applications. The 6 mA setting should be ...
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The ADAU144x is able to operate in a flexible TDM mode, which allows it to interface to a wide variety of digital audio devices. SERIAL INPUT FLEXIBLE TDM INTERFACE MODES AND SETTINGS The flexible TDM mode is available for the ...
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Flexible TDM to Input Channel Modes Registers (Address 0xE180 to Address 0xE197) Table 72. Addresses of Serial Input Flexible TDM Interface Modes Registers Address Decimal Hex Name 57728 E180 Flexible TDM to Input Channel 0 57729 E181 Flexible TDM to ...
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SERIAL OUTPUT FLEXIBLE TDM INTERFACE MODES AND SETTINGS The flexible TDM mode used on the SDATA_IN[1:0] serial input ports can also be used on the SDATA_OUT[1:0] serial output ports. There are 24 output channels available to the output ports in ...
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OUTPUT CHANNELS (24 CH) ... SDATA_OUT0 ...
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Address Decimal Hex Name 57821 E1DD TDM Slot 58 and TDM Slot 59 (SDATA_OUT1) 57822 E1DE TDM Slot 60 and TDM Slot 61 (SDATA_OUT1) 57823 E1DF TDM Slot 62 and TDM Slot 63 (SDATA_OUT1) 1 Slot 31 and Slot 63 ...
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SOFTWARE SAFELOAD In order to update parameters in real time while avoiding pop and click noises on the output, the ADAU144x uses a software safeload mechanism. SigmaStudio sets up the necessary code and parameters automatically for new projects. The safeload ...
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... This section contains a list of all RAMS and registers. OVERVIEW OF REGISTER ADDRESS MAP Table 78. ADAU1442/ADAU1445/ADAU1446 RAM and Register Map Address Decimal Start Value End Value Start Value 0 4095 0000 8192 12287 2000 16384 24575 4000 57344 57352 E000 57408 57417 E040 57472 ...
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Table 82. Serial Input Port Modes Registers Address Decimal Hex 57344 E000 57345 E001 57346 E002 57347 E003 57348 E004 57349 E005 57350 E006 57351 E007 57352 E008 Table 83. Serial Output Port Modes Registers Address Decimal Hex Name 57408 ...
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Address Decimal Hex Name Serial output select, Pair 3 (Channel 6, Channel 7) 57491 E093 57492 E094 Serial output select, Pair 4 (Channel 8, Channel 9) 57493 E095 Serial output select, Pair 5 (Channel 10, Channel 11) 57494 E096 Serial ...
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Address Decimal Hex Name 57736 E188 Flexible TDM to Input Channel 8 57737 E189 Flexible TDM to Input Channel 9 57738 E18A Flexible TDM to Input Channel 10 57739 E18B Flexible TDM to Input Channel 11 57740 E18C Flexible TDM ...
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Address Decimal Hex Name 57821 E1DD TDM Slot 58 and TDM Slot 59 (SDATA_OUT1) 57822 E1DE TDM Slot 60 and TDM Slot 61 (SDATA_OUT1) 57823 E1DF TDM Slot 62 and TDM Slot 63 (SDATA_OUT1) Table 89. Other Modes Registers Address ...
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... A single ground plane should be used in the application layout. Components in an analog signal path should be placed away from digital signals. Exposed Pad PCB Design The ADAU1442 and ADAU1445 packages include an exposed pad for improved heat disippation. When designing a board for such a package, special consideration should be given to the following: • ...
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... D3V3 AVDD PVDD IOVDD DVDD + + + + 10μF 10μF 10μF 10μF Figure 63. Recommended Power Supply Bypass Capacitor Connections IOVDD IOVDD DVDD 100nF 100nF ADAU1442/ADAU1445/ADAU1446 AVDD 100nF 100nF 100nF 100nF DVDD IOVDD PVDD Rev. PrA| Page 100nF 100nF DVDD DVDD ...
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... PVDD IOVDD + + 10μF 10μF DVDD IOVDD 100nF 1 DGND 2 IOVDD 3 BCLK3 4 LRCLK3 5 SDATA_IN2 6 BCLK2 7 LRCLK2 8 SDATA_IN1 9 BCLK1 10 LRCLK1 11 SDATA_IN0 12 BCLK0 ADAU1442/ADAU1445/ADAU1446 13 DGND 14 IOVDD 15 LRCLK0 16 MP11 17 MP10 18 MP9 19 MP8 20 ADDR0 21 CLATCH 22 SCL/CCLK 23 SDA/COUT 24 ADDR1/CDATA 25 DVDD DVDD 10kΩ 100nF 100nF DVDD DVDD IOVDD ...
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... IOVDD D3V3 AVDD PVDD IOVDD DVDD + + + + 10μF 10μF 10μF 10μF Figure 65. I IOVDD IOVDD DVDD 100nF 100nF ADAU1442/ADAU1445/ADAU1446 AVDD 10kΩ 100nF 100nF 100nF 100nF DVDD IOVDD PVDD 33nF 22pF 22pF 1.5kΩ PVDD DVDD 1kΩ D3V3 REGULATOR 2 C Control Application Schematic Rev ...
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... IOVDD D3V3 AVDD PVDD IOVDD DVDD + + + + 10μF 10μF 10μF 10μF Figure 66. SPI Control Application Schematic IOVDD DVDD 100nF 100nF ADAU1442/ADAU1445/ADAU1446 AVDD 10kΩ 100nF 100nF 100nF DVDD IOVDD PVDD DVDD SELF 1kΩ 22pF 22pF BOOT SWITCH DVDD 1kΩ D3V3 REGULATOR Rev. PrA | Page ...
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... FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD Figure 67. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-8) Used for ADAU1442 and ADAU1445 Dimensions shown in millimeters 1.60 MAX 0.75 100 1 0.60 ...
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... C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, provided that the system conforms to the I ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07696-0-10/08(PrA Standard Specification as defined by Philips ...