adau1961 Analog Devices, Inc., adau1961 Datasheet
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adau1961 Summary of contents
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... Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL GENERAL DESCRIPTION The ADAU1961 is a low power, stereo audio codec that supports stereo 48 kHz record and playback from a 3.3 V analog supply. The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control ...
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... ADAU1961 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Analog Performance Specifications, T Analog Performance Specifications, −40°C < T Power Supply Specifications........................................................ 7 Digital Filters ................................................................................. 8 Digital Input/Output Specifications........................................... 8 Digital Timing Specifications ..................................................... 9 Digital Timing Diagrams........................................................... 10 Absolute Maximum Ratings .......................................................... 12 Thermal Resistance .................................................................... 12 ESD Caution ...
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... RINPG[2:0], RINNG[2:0] = 000, MX1AUXG[2:0], MX2AUXG[2:0] = 000 CM capacitor = 20 μF, 100 mV p kHz kHz, −60 dB input −1 dBFS 20 dB gain setting (RDBOOST[1:0], LDBOOST[1:0] = 10) Rev Page ADAU1961 mode), input sample rate = 48 kHz, measurement S (digital output mA LOAD IH Min Typ ...
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... ADAU1961 Parameter Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Common-Mode Rejection Ratio FULL DIFFERENTIAL PGA INPUT Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) ...
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... CM capacitor = 20 μF, 100 mV p kHz CM pin < +105°C A Test Conditions/Comments kHz, −60 dB input −1 dBFS − range LINPG[2:0], LINNG[2:0] = 000, RINPG[2:0], RINNG[2:0] = 000, MX1AUXG[2:0], MX2AUXG[2:0] = 000 Rev Page ADAU1961 Min Typ Max −92 −77 −89 −79 101 98 −85 −78 − ...
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... ADAU1961 Parameter PSEUDO-DIFFERENTIAL PGA INPUT Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise PGA Boost Gain Error Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Common-Mode Rejection Ratio FULL DIFFERENTIAL PGA INPUT Dynamic Range With A-Weighted Filter (RMS) ...
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... kHz S PLL bypass Integer PLL 10 kΩ load PLL bypass Integer PLL 32 Ω load PLL bypass Integer PLL 32 Ω load PLL bypass Integer PLL Rev Page ADAU1961 Min Typ Max −0.3 +0.3 −22 +22 −10 +10 −61 −63 −76 1.47 1.83 Min Typ Max 1 ...
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... ADAU1961 DIGITAL FILTERS Table 4. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < T < +105°C, IOVDD = 3.3 V ± 10%. ...
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... MΩ, C LOAD 10 ns Digital microphone clock fall time Digital microphone clock rise time Digital microphone delay time for valid data Digital microphone delay time for data three-stated. Rev Page ADAU1961 mode. S mode. S mode. S mode pF. LOAD ...
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... ADAU1961 DIGITAL TIMING DIAGRAMS t BIH BCLK t BIL t LIS LRCLK t SIS DAC_SDATA LEFT-JUSTIFIED MSB MODE t SIH DAC_SDATA MODE DAC_SDATA RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) t BIH BCLK t BIL LRCLK ...
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... CCPL t CDH Figure 4. SPI Port Timing SCR SCLH SCS SCLL SCF 2 Figure Port Timing t t DCF DCR t t DDH DDH t DDV DATA2 DATA1 DATA2 Figure 6. Digital Microphone Timing Rev Page ADAU1961 t CLH t CLPH t COD t SCH t BFT t DDV ...
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... ADAU1961 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Power Supply (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...
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... LOUTP AVDD 8 17 LOUTN NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1961 GROUNDS. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 7. Pin Configuration Description Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD, which also sets the highest input voltage that should be seen on the digital input pins ...
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... SPI Clock (CCLK). This pin can run continuously or be gated off between SPI transactions. Exposed Pad. The exposed pad is connected internally to the ADAU1961 grounds. For increased reliability of the solder joints and maximum thermal capability recommended that the pad be soldered to the ground plane ...
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... DIGITAL 1kHz INPUT SIGNAL (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –60 –50 –40 –30 –20 DIGITAL 1kHz INPUT SIGNAL (dBFS) 0.04 0.02 0 −0.02 −0.04 −0.06 0 0.05 0.10 0.15 0.20 0.25 0.30 FREQUENCY (NORMALIZED TO Normalized ADAU1961 –10 0 –10 0 0.35 0. ...
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... ADAU1961 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 14. ADC Decimation Filter, 128× Oversampling, Normalized −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 15. ADC Decimation Filter, 128× Oversampling, Double-Rate Mode, ...
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... Figure 23. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling, S 0.20 0.15 0.10 0.05 −0.05 −0.10 −0.15 −0.20 0.7 0.8 0.9 1 Figure 24. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling, Rev Page 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 f FREQUENCY (NORMALIZED Normalized 0.05 0.10 0.15 0.20 0.25 0.30 f FREQUENCY (NORMALIZED Double-Rate Mode, Normalized ADAU1961 0.45 0.50 0.35 0.40 ...
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... AUX RIGHT 1kΩ CLOCK SOURCE FROM VOLTAGE REGULATOR (1.8V TO 3.3V) 10µF 10µ 0.1µF 0.1µF DVDDOUT IOVDD LINP LINN ADAU1961 MICBIAS RINN RINP JACKDET/MICIN 10µF LAUX 10µF RAUX 49.9Ω MCLK Figure 25. System Block Diagram Rev Page 10µF + 0.1µF 0.1µF 1.2nH 9 ...
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... DVDDOUT IOVDD AVDD AVDD MICBIAS LINN LINP ADAU1961 RINN RINP ADC_SDATA JACKDET/MICIN DAC_SDATA LAUX ADDR1/CDATA RAUX ADDR0/CLATCH MCLK Rev Page ADAU1961 10µF + 0.1µF 0.1µF 1.2nH 9.1pF LOUTP EARPIECE SPEAKER LOUTN RHP CAPLESS HEADPHONE MONOOUT OUTPUT LHP ROUTP EARPIECE SPEAKER ...
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... DVDDOUT IOVDD AVDD AVDD MICBIAS RHP MONOOUT LHP LINP LINN RINN RINP LOUTP ADAU1961 LOUTN ROUTP ROUTN JACKDET/MICIN ADC_SDATA DAC_SDATA LAUX LRCLK BCLK RAUX ADDR1/CDATA SDA/COUT SCL/CCLK MCLK ADDR0/CLATCH CM Rev Page 10µF + 9.1pF ...
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... The ADAU1961 can generate its internal clocks from a wide range of input clocks by using the on-board fractional PLL. The PLL accepts inputs from 8 MHz to 27 MHz. The ADAU1961 is provided in a small, 32-lead × LFCSP with an exposed bottom pad. Rev Page ...
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... The POR monitors the DVDDOUT pin and generates a reset signal whenever power is applied to the chip. During the reset, the ADAU1961 is set to the default values documented in the register map (see the Control Registers section). Typically, with a 10 μF capacitor on AVDD, the POR takes approximately 14 ms ...
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... PLL has locked. After lock is acquired, the ADAU1961 can be started by asserting the core clock enable bit (COREN) in Register R0 (clock control register, Address 0x4000). This bit enables the core clock to all the internal blocks of the ADAU1961. PLL Lock Acquisition During the lock acquisition period, only Register R0 (Address 0x4000) and Register R1 (Address 0x4002) are accessible through the control port ...
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... ADAU1961 CLOCKING AND SAMPLING RATES R1: PLL CONTROL REGISTER MCLK ÷ X × N/M) CORE CLOCK Clocks for the converters and the serial ports are derived from the core clock. The core clock can be derived directly from MCLK or it can be generated by the PLL. The CLKSRC bit (Bit 3 in Register R0, Address 0x4000) determines the clock source ...
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... Table 15 and Table 16. TO PLL CLOCK DIVIDER The PLL outputs a clock in the range of 41 MHz to 54 MHz, which should be taken into account when calculating PLL values and MCLK frequencies kHz, then S Rev Page ADAU1961 = 48 kHz, then S ...
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... ADAU1961 Table 15. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider ( 14.4 2 19.2 2 19. Table 16. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider ( 14.4 2 19.2 2 19. Table 17. Integer PLL Parameter Settings for f ...
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... RDVOL[5:0] ALC CONTROL INPUT SIGNAL PATHS The ADAU1961 can accept both line level and microphone inputs. The analog inputs can be configured in a single-ended or differential configuration. There is also an input for a digital microphone. The analog inputs are biased at AVDD/2. Unused input pins should be connected to CM. ...
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... RDBOOST[1:0] Figure 34. Stereo Single-Ended Line Input with Stereo Auxiliary Bypass MUTE/ 0dB/20dB ADAU1961 LDBOOST[1:0] MUTE/ 0dB/20dB RDBOOST[1:0] MUTE/ 0dB/20dB Rev Page ADAU1961 LINNG[2:0] LINN LEFT LINE INPUT –12dB TO +6dB LAUX LEFT AUX INPUT AUXILIARY BYPASS RAUX RIGHT AUX INPUT ...
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... ADC Full-Scale Level The full-scale input to the ADCs (0 dBFS) is 1.0 V rms with AVDD = 3.3 V. This full-scale analog input will output a digital signal at −1.38 dBFS. This gain offset is built into the ADAU1961 to prevent clipping. The full-scale input level scales linearly with the level of AVDD. ...
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... ADAU1961 AUTOMATIC LEVEL CONTROL (ALC) The ADAU1961 contains a hardware automatic level control (ALC). The ALC is designed to continuously adjust the PGA gain to keep the recording volume constant as the input level varies. For optimal noise performance, the ALC uses the analog PGA to adjust the gain instead of using a digital method. This ensures that the ADC noise is not amplified at low signal levels ...
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... This causes an unpleasant sound. To reduce this effect, the noise gate in the ADAU1961 uses a combination of a timeout period and hysteresis. The timeout period is set to 250 ms, so the signal must consistently be below the threshold for 250 ms before the noise gate operates ...
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... NGTYP[1:0] bits to 10. In this mode, the ADAU1961 improves the sound of the noise gate operation by first fading the PGA gain over a period of about 100 ms to the minimum PGA gain value. The ADAU1961 does not do a hard mute after the fade is complete, so some small background noise will still exist. THRESHOLD ...
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... TO +6dB LEFT DAC RIGHT DAC OUTPUT SIGNAL PATHS The outputs of the ADAU1961 can be configured as a variety of differential or single-ended outputs. All analog output pins are capable of driving headphone or earpiece speakers. There are selectable output paths for stereo signals or a downmixed mono output. The line outputs can drive a load of at least 10 kΩ ...
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... ADAU1961 HEADPHONE OUTPUT The LHP and RHP pins can be driven by either a line output driver or a headphone driver by setting the HPMODE bit in Register R30 (playback headphone right volume control register, Address 0x4024). The headphone outputs can drive a load of at least 16 Ω. Separate volume controls for the left and right channels range from − ...
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... Address 0x4020) and Register R27 (playback L/R mixer right (Mixer 6) line output control register, Address 0x4021). MX5G3[1:0] MIXER 3 LEFT DAC MX6G4[1:0] MIXER 4 RIGHT DAC Figure 47. Differential Line Output Configuration Rev Page ADAU1961 LOUTVOL[5:0] MIXER 5 LOUTP –1 LOUTN –1 ROUTN ROUTVOL[5:0] MIXER 6 ...
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... ADAU1961 and the system mode, the ADAU1961 is always a slave on the bus, meaning that it cannot initiate a data transfer. Each slave device is recognized by a unique address. The address and R/ W byte format is shown in ...
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... ADAU1961 does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while in autoincrement mode, one of two actions is taken. In read mode, the ADAU1961 outputs the highest subaddress register contents until the master 2 C write, device issues a no acknowledge, indicating the end of a read ...
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... AS Subaddress R high byte This causes the ADAU1961 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1961. Figure 53 shows the format of a burst mode read sequence. This figure shows an example of a read from sequential single-byte registers ...
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... ADAU1961 does not acknowledge these three writes). Beginning with the fourth SPI write, data can be written to or read from the IC. The ADAU1961 can be taken out of SPI mode only by a full reset initiated by power-cycling the IC. The SPI port uses a 4-wire interface, consisting of the CLATCH , CCLK, CDATA, and COUT signals, and it is always a slave port ...
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... Figure 61) The serial port can operate with an arbitrary number of BCLK transitions in each LRCLK frame. The LRCLK in TDM mode can be input to the ADAU1961 either as a 50% duty cycle clock bit-wide pulse. When the LRCLK is set as a pulse capacitor should be connected between the LRCLK pin and ground (see Figure 56). ...
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... S LSB 128 BCLKs SLOT 1 SLOT 2 LRCLK BCLK SDATA MSB MSB – 1 MSB – 2 Figure 60. TDM 4 Mode SLOT 1 SLOT 2 Figure 61. TDM 4 Mode with Pulse Word Clock Rev Page ADAU1961 LSB RIGHT CHANNEL LSB RIGHT CHANNEL MSB LSB SLOT 3 SLOT 3 ...
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... Components in an analog signal path should be placed away from digital signals. EXPOSED PAD PCB DESIGN The ADAU1961 has an exposed pad on the underside of the LFCSP. This pad is used to couple the package to the PCB for heat dissipation when using the outputs to drive earpiece or headphone loads ...
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... ROUTVOL[5:0] MONOVOL[5:0] Reserved POPMODE Reserved DACMONO[1:0] DACPOL Reserved LDAVOL[7:0] RDAVOL[7:0] ADCSDP[1:0] DACSDP[1:0] CDATP[1:0] CLCHP[1:0] Reserved Reserved JDSTR Reserved DEJIT[7:0] Rev Page ADAU1961 Bit 3 Bit 2 Bit 1 Bit 0 CLKSRC INFREQ[1:0] COREN X[1:0] Type Lock PLLEN Reserved JDPOL LINNG[2:0] MX1EN MX1AUXG[2:0] RINNG[2:0] MX2EN MX2AUXG[2:0] ...
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... ADAU1961 CONTROL REGISTER DETAILS All registers except for the PLL control register are 1-byte write and read registers. R0: Clock Control, 16,384 (0x4000) Bit 7 Bit 6 Bit 5 Reserved Table 26. Clock Control Register Bits Bit Name Description 3 CLKSRC Clock source select direct from MCLK pin (default). ...
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... Lock PLL lock. This read-only bit is flagged when the PLL has finished locking PLL unlocked (default PLL locked PLLEN PLL enable PLL disabled (default PLL enabled. Value (default Value (default Rev Page ADAU1961 ...
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... ADAU1961 R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008) Bit 7 Bit 6 Bit 5 JDDB[1:0] Table 28. Digital Microphone/Jack Detection Control Register Bits Bit Name Description [7:6] JDDB[1:0] Jack detect debounce time. Setting [5:4] JDFUNC[1:0] JACKDET/MICIN pin function. Enables or disables the jack detect function or configures the pin for a digital microphone input ...
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... Left single-ended auxiliary input gain from the LAUX pin in the record path, input to Mixer 1. Setting 000 001 010 011 100 101 110 111 Bit 4 Bit 3 Bit 2 LDBOOST[1:0] Gain Boost Mute (default Reserved Auxiliary Input Gain Mute (default) −12 dB −9 dB −6 dB − Rev Page ADAU1961 Bit 1 Bit 0 MX1AUXG[2:0] ...
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... ADAU1961 R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) This register controls the gain of single-ended inputs for the right channel record path. The right channel record mixer is referred to as Mixer 2. Bit 7 Bit 6 Bit 5 Reserved RINPG[2:0] Table 31. Record Mixer Right (Mixer 2) Control 0 Register ...
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... Mute (default Reserved Auxiliary Input Gain Mute (default) −12 dB −9 dB −6 dB − Bit 4 Bit 3 LDVOL[5:0] Volume −12 dB (default) −11.25 dB … … 34.5 dB 35.25 dB Rev Page ADAU1961 Bit 2 Bit 1 Bit 0 MX2AUXG[2:0] Bit 2 Bit 1 Bit 0 LDMUTE LDEN ...
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... ADAU1961 R9: Right Differential Input Volume Control, 16,399 (0x400F) This register enables the differential path and sets the volume control for the right differential PGA input. Bit 7 Bit 6 Bit 5 Table 34. Right Differential Input Volume Control Register Bits Bit Name Description [7:2] RDVOL[5:0] Right channel differential PGA input volume control. The right differential input uses the RINP (positive signal) and RINN (negative signal) pins ...
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... Bit 3 Bit 2 ALCMAX[2:0] Slew Time 24 ms (default Off Maximum ALC Gain −12 dB (default) − Channels Off (default) Right only Left only Stereo Reserved Reserved Reserved Reserved Rev Page ADAU1961 Bit 1 Bit 0 ALCSEL[2:0] ...
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... ADAU1961 R12: ALC Control 1, 16,402 (0x4012) Bit 7 Bit 6 Bit 5 ALCHOLD[3:0] Table 37. ALC Control 1 Register Bits Bit Name Description [7:4] ALCHOLD[3:0] ALC hold time. The ALC hold time is the amount of time that the ALC waits after a decrease in input level before increasing the gain to achieve the target level. The recommended minimum setting (0011) to prevent distortion of low frequency signals ...
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... Decay Time 192 ms 384 ms 768 ms 1.54 sec 3.07 sec 6.14 sec 12.29 sec 24.58 sec 49.15 sec 98.30 sec 196.61 sec 393.22 sec 786.43 sec Rev Page ADAU1961 Bit 1 Bit 0 ALCDEC[3:0] ...
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... ADAU1961 R14: ALC Control 3, 16,404 (0x4014) Bit 7 Bit 6 Bit 5 NGEN NGTYP[1:0] Table 39. ALC Control 3 Register Bits Bit Name Description [7:6] NGTYP[1:0] Noise gate type. When the input signal falls below the threshold for 250 ms, the noise gate can hold a constant PGA gain, mute the ADC output, fade the PGA gain to the minimum gain value, or fade then mute. ...
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... LRDEL[1:0] Data delay from LRCLK edge (in BCLK units). Setting Bit 4 Bit 3 Bit 2 ADTDM DATDM MSBP Bit Clock Cycles 64 (default 128 256 Reserved Reserved Reserved Delay (Bit Clock Cycles) 1 (default Rev Page ADAU1961 Bit 1 Bit 0 LRDEL[1:0] ...
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... ADAU1961 R17: Converter Control 0, 16,407 (0x4017) Bit 7 Bit 6 Bit 5 Reserved DAPAIR[1:0] Table 42. Converter Control 0 Register Bits Bit Name Description [6:5] DAPAIR[1:0] On-chip DAC serial data selection in TDM mode. Setting DAOSR DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz. ...
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... Bit 4 Bit 3 Bit 2 DMPOL DMSW INSEL = 2 Hz. 3dB ADCs Enabled Both off (default) Left on Right on Both on Bit 4 Bit 3 Bit 2 LADVOL[7:0] Volume Attenuation 0 dB (default) −0.375 dB −0.75 dB … −95.25 dB −95.625 dB Rev Page ADAU1961 Bit 1 Bit 0 ADCEN[1:0] , and S Bit 1 Bit 0 ...
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... ADAU1961 R21: Right Input Digital Volume, 16,411 (0x401B) Bit 7 Bit 6 Bit 5 Table 46. Right Input Digital Volume Register Bits Bit Name Description [7:0] RADVOL[7:0] Controls the digital volume attenuation for right channel inputs from either the right ADC or the right digital microphone input. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 71 for a complete list of the volume settings ...
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... Bit 4 Bit 3 Bit 2 Gain Mute (default) −15 dB −12 dB −9 dB −6 dB − Gain Mute (default) −15 dB −12 dB −9 dB −6 dB − Rev Page ADAU1961 Bit 1 Bit 0 MX3G1[3:0] ...
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... ADAU1961 R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) Bit 7 Bit 6 Bit 5 Reserved MX4RM MX4LM Table 49. Playback Mixer Right (Mixer 4) Control 0 Register Bits Bit Name Description 6 MX4RM Mixer input mute. Mutes the right DAC input to the right channel playback mixer (Mixer 4). ...
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... Reserved Gain Boost Mute (default output (−6 dB gain on each of the two inputs output (0 dB gain on each of the two inputs) Reserved Rev Page ADAU1961 Bit 1 Bit 0 MX4G1[3:0] Bit 1 Bit 0 MX5EN MX5G3[1:0] ...
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... ADAU1961 R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021) Bit 7 Bit 6 Bit 5 Reserved Table 52. Playback L/R Mixer Right (Mixer 6) Line Output Control Register Bits Bit Name Description [4:3] MX6G4[1:0] Mixer input gain boost. The signal from the right channel playback mixer (Mixer 4) can be enabled and boosted in the playback L/R mixer right (Mixer 6) ...
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... Bit 4 Bit 3 LHPVOL[5:0] Volume −57 dB (default) … … Bit 4 Bit 3 RHPVOL[5:0] Volume −57 dB (default) … … Rev Page ADAU1961 Bit 2 Bit 1 Bit 0 LHPM HPEN Bit 2 Bit 1 Bit 0 RHPM HPMODE ...
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... ADAU1961 R31: Playback Line Output Left Volume Control, 16,421 (0x4025) Bit 7 Bit 6 Bit 5 Table 56. Playback Line Output Left Volume Control Register Bits Bit Name Description [7:2] LOUTVOL[5:0] Line output volume control for left channel, LOUTN and LOUTP outputs. Each 1-bit step corresponds increase in volume ...
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... Bit 4 Bit 3 MONOVOL[5:0] Volume −57 dB (default) … … Bit 4 Bit 3 POPMODE POPLESS Slew Rate 21.25 ms (default) 42 Off Bit 4 Bit 3 Reserved Rev Page ADAU1961 Bit 2 Bit 1 Bit 0 MONOM MOMODE Bit 2 Bit 1 Bit 0 ASLEW[1:0] Reserved Bit 2 Bit 1 Bit 0 PREN PLEN ...
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... ADAU1961 R36: DAC Control 0, 16,426 (0x402A) Bit 7 Bit 6 Bit 5 DACPOL DACMONO[1:0] Table 61. DAC Control 0 Register Bits Bit Name Description [7:6] DACMONO[1:0] DAC mono mode. The DAC channels can be set to mono mode within the DAC and output on the left channel, the right channel, or both channels. ...
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... Bit 4 Bit 3 DACSDP[1:0] LRCLKP[1:0] Configuration Pull-up Reserved None (default) Pull-down Configuration Pull-up Reserved None (default) Pull-down Configuration Pull-up Reserved None (default) Pull-down Configuration Pull-up Reserved None (default) Pull-down Rev Page ADAU1961 Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 BCLKP[1:0] ...
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... ADAU1961 R40: Control Port Pad Control 0, 16,431 (0x402F) The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the control port signals to a defined state when the signal source becomes three-state. Bit 7 Bit 6 Bit 5 CDATP[1:0] Table 65 ...
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... DEJIT[7:0] Dejitter window size. Window Size 00000000 … 00000011 … 00000101 Bit 4 Bit 3 Bit 2 Reserved JDP[1:0] Configuration Pull-up Reserved None (default) Pull-down Bit 4 Bit 3 Bit 2 DEJIT[7:0] Core Clock Cycles 0 … 3 (default) … 5 Rev Page ADAU1961 Bit 1 Bit 0 Reserved Bit 1 Bit 0 ...
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... ADAU1961 Table 69. R8 and R9 Volume Settings Binary Value Volume Setting (dB) 000000 −12 000001 −11.25 000010 −10.5 000011 −9.75 000100 −9 000101 −8.25 000110 −7.5 000111 −6.75 001000 −6 001001 −5.25 001010 −4.5 001011 −3.75 001100 −3 001101 −2.25 001110 −1.5 001111 − ...
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... Rev Page ADAU1961 Volume Attenuation (dB) −18 −18.375 −18.75 −19.125 −19.5 −19.875 −20.25 −20.625 −21 −21.375 −21.75 −22.125 −22.5 −22.875 − ...
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... ADAU1961 Binary Value Volume Attenuation (dB) 01100000 −36 01100001 −36.375 01100010 −36.75 01100011 −37.125 01100100 −37.5 01100101 −37.875 01100110 −38.25 01100111 −38.625 01101000 −39 01101001 −39.375 01101010 −39.75 01101011 −40.125 01101100 −40.5 01101101 −40.875 01101110 − ...
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... Rev Page ADAU1961 Volume Attenuation (dB) −91.125 −91.5 −91.875 −92.25 −92.625 −93 −93.375 −93.75 −94.125 −94.5 −94.875 −95.25 −95.625 Volume Setting (dB) − ...
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... ADAU1961 Binary Value Volume Setting (dB) 100001 −24 100010 −23 100011 −22 100100 −21 100101 −20 100110 −19 100111 −18 101000 −17 101001 −16 101010 −15 101011 −14 101100 −13 101101 −12 101110 −11 101111 −10 110000 −9 110001 −8 110010 −7 110011 − ...
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... W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADAU1961 models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications ...
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... ADAU1961 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08915-0-10/10(0) Rev Page ...