lm4549a National Semiconductor Corporation, lm4549a Datasheet
lm4549a
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lm4549a Summary of contents
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... AC ’97 Rev 2.1 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound General Description The LM4549A is an audio codec for PC systems which is fully PC99 compliant and performs the analog intensive functions of the AC ’97 Rev 2.1 architecture. Using 18-bit Sigma-Delta ADCs and DACs, the LM4549A provides Dynamic Range ...
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... All Analog Inputs CD Left to Right 22 -34 ≤ T (Note 4) −40˚C ≤ MAX 4.2V ≤ 3.0V ≤ 5V 5V 25˚C. The reference for Vrms un- LM4549A Typical Limit (Note 6) (Note 7) 4.2 5.5 3.0 5 500 30 2. kΩ ...
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... Variation of BIT_CLK duty cycle from 50% SDATA_OUT to falling edge of BIT_CLK Hold time of SDATA_OUT from falling edge of BIT_CLK SYNC to rising edge of BIT_CLK Hold time of SYNC from rising edge of BIT_CLK Units LM4549A (Limits) Typical Limit (Note 6) (Note 7) 18 Bits (min) 20 kHz 18 ...
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... Delay from end of Slot 2 to BIT_CLK, SDATA_IN low Time from minimum valid supply levels to end of Reset For ATE Test Mode For ATE Test Mode )/θ or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4549A 5V 5V ...
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Timing Diagrams Clocks Digital Rise and Fall www.national.com Data Delay, Setup and Hold 20029910 20029912 Power On Reset Cold Reset Warm Reset 6 20029911 Legend 20029930 20029929 20029913 20029914 ...
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... Typical Application FIGURE 1. LM4549A Typical Application Circuit, Single Codec, 1 Vrms inputs APPLICATION HINTS • The LM4549A must be initialized by using RESET# to perform a Power On Reset as shown in the Power On Reset Timing Diagram • V must be pulled high to AV with a 10 kΩ resistor to ensure correct operation ...
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... The PHONE level can be muted or adjusted from + -34 1.5 dB steps. The Stereo Mix signal feeds both the Line Out and Line Level Out analog stereo outputs and is also selectable at the Record Select Mux. Top View Order Number LM4549AVH See NS Package Number VBH48A ANALOG I/O 9 20029902 www ...
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Pin Descriptions (Continued) Name Pin Functional Description Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. ...
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Pin Descriptions (Continued) Name Pin Functional Description Mono microphone input Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit D8) in the General Purpose register, 20h. The ...
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... This pin is an INPUT when the codec is configured in any of the Secondary Codec modes and would normally use the AC Link clock generated by a Primary Codec. Output from codec This is the output for AC Link Input Frames from the LM4549A codec ’97 Digital SDATA_IN 8 O Audio Controller ...
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... Pin Cold Reset This active low signal causes a hardware reset which returns the control registers and all internal circuits to their default conditions. RESET# must be used to initialize the LM4549A RESET after Power On when the supplies have stabilized. Cold Reset also clears the codec from both ATE and Vendor test modes ...
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Pin Descriptions (Continued) Name Pin 29, 30 31, 32 These pins are not used and should be left open (NC For second source applications these pins may be connected to a noise-free supply ...
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Volume Output Volume Input Sources ADC 15 www.national.com ...
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... Functional Description GENERAL The LM4549A codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format) inputs and outputs. There are four stereo and four mono analog inputs and two stereo and one mono analog outputs. A single codec supports data streaming on two input and two output channels of the AC Link digital interface simultaneously ...
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... Data Slots. With the codec in Primary mode, a controller will indicate valid data in a slot by setting the associated tag bit equal to 1. Since two channel codec the LM4549A can only receive data from four slots in a given frame and so only 17 ...
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... SDATA_OUT: Slot 2 – Control Data Slot 2 is used to transmit 16-bit control data to the LM4549A when the access operation is ’write’. The least significant four bits should be stuffed with zeros by the AC ’97 controller. If the access operation is a register read, the entire slot, bits 19 through 0 should be stuffed with zeros ...
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... Frames are constructed from thirteen time slots: one Tag Slot followed by twelve Data Slots. The Tag Slot, Slot 0, contains 16 bits of which 5 are used by the LM4549A. One is used to indicate that the AC Link interface is fully operational and the other 4 to indicate the validity of the data in the four of the twelve following Data Slots that are used by the LM4549A ...
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... Hz, then only those one-in-six audio samples that follow a Slot Request will be used by the DAC. The rest will be discarded. Bits 9 – 2 are request bits for slots not used by the LM4549A and are stuffed with zeros. Bits 1 and 0 are reserved and are also stuffed with zeros. ...
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... PCM sample from right 19:2 Right Channel ADC data 1:0 Reserved Stuffed with "0"s by LM4549A SDATA_IN: Slots – Reserved Slots 5 – the AC Link Input Frame are not used for data by the LM4549A and are always stuffed with zeros. 21 Comment www.national.com ...
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... RESET REGISTER (00h) Writing any value to this register causes a Register Reset which changes all registers back to their default values read is performed on this register, the LM4549A will return a value of 0D40h. This value can be interpreted in accordance with the AC ’97 Specification to indicate that National 3D Sound is implemented and 18-bit data is supported for both the ADCs and DACs ...
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... Default: 000Xh EXTENDED AUDIO ID REGISTER (28h) This read-only (X001h) register identifies which AC ’97 Ex- tended Audio features are supported. The LM4549A features VRA (Variable Rate Audio) and ID1, ID0 (Multiple Codec support). VRA is indicated by a "1" in bit 0. The two MSBs, ID1 and ID0, show the current Codec Identity as defined by the Identity pins ID1#, ID0# ...
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... Low Power Modes The LM4549A provides 6 bits to control the powerdown state of internal analog and digital subsections and clocks. It also provides one bit intended to control an external analog power amplifier. These 7 bits (PR0 – PR5, EAPD) are lo- cated in the 8 MSBs of the Powerdown Control/Status reg- ister, 26h ...
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Low Power Modes (Continued) Improving System Performance The audio codec is capable of dynamic range performance in excess of 90 db., but the user must pay careful attention to several factors to achieve this. A primary consideration is keeping analog ...
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Multiple Codecs (Continued) When reading from a Secondary Codec, the controller must send the correct Codec ID bits ( i.e. the target Codec Identity in slot 0, bits 1 and 0) along with the read-request bit (slot 1, bit 19) ...
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Multiple Codecs (Continued) FIGURE 9. Multiple Codecs using Extended AC Link Test Modes AC ’97 Rev 2.1 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit either of them. The ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted 48-Lead , LQFP 1.4mm, JEDEC (M) Order Number LM4549AVH NS Package Number VBH48A 2. A critical component is any component of a life ...