isp1504a1 NXP Semiconductors, isp1504a1 Datasheet
isp1504a1
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isp1504a1 Summary of contents
Page 1
... ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver Rev. 01 — 6 August 2007 1. General description The ISP1504A1; ISP1504C1 (ISP1504x1 Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 , On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2 and UTMI+ Low Pin Interface (ULPI) Specifi ...
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... I Highly optimized ULPI-compliant interface N 60 MHz, 8-bit interface between the core and the transceiver N Integrated Phase-Locked Loop (PLL) supporting input clock frequency of 19.2 MHz for ISP1504A1, and 26 MHz for ISP1504C1 N Fully programmable ULPI-compliant register set N Internal Power-On Reset (POR) circuit I Flexible system integration and very low current consumption, optimized for portable ...
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... ISP1504C1ET 504P 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Package Name Description TFBGA36 plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 3.5 Rev. 01 — 6 August 2007 ...
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... F5 XTAL1 F6 XTAL2 B2, B3, B5 interface voltage V CC(I/O) E3 REG3V3 E6 REG1V8 Fig 1. Block diagram ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 USB DATA SERIALIZER ULPI INTERFACE CONTROLLER USB DATA DESERIALIZER V valid external BUS REGISTER MAP Drive V external BUS POWER-ON global RESET reset ...
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... ULPI data bus slew rate controlled output (1 ns); plain input; programmable pull down data minus (D ) pin of the USB cable resistor reference; connect through 12 k Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver ISP1504x1 ...
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... V BUS except when the ISP1504x1 is used as a host-only with an external 5 V source crystal oscillator or clock input; 1.8 V peak input allowed; frequency is 19.2 MHz for ISP1504A1, and 26 MHz for ISP1504C1 crystal oscillator output; if crystal is not in use, leave this pin open Section 7.9. ...
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... USB peripheral, host and OTG implementations. The following circuitry is included: • Differential drivers to transmit data at high-speed, full-speed and low-speed ISP1504A1_ISP1504C1_1 Product data sheet external power source BUS monitoring, charging and discharging Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Section 9. © NXP B.V. 2007. All rights reserved ...
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... This module contains several sub-blocks that provide all the functionality required by the USB OTG specification. Specifically, it provides the following circuits: ISP1504A1_ISP1504C1_1 Product data sheet high-speed bus terminations on DP and DM pin CC Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Table 8. < 4 < 3.5 V, drawing power CC ...
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... Any voltage on V A_VBUS_VLD , with a hysteresis of V hys(A_SESS_VLD) power. First, the B-device makes sure that V BUS Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver voltage level. This is required for the V BUS . This is required for SRP. BUS valid comparator, session valid BUS voltage level ...
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... V is present, the chip is put in power-down mode. CC Section 15. This provides an accurate voltage reference that Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver 1 % resistor must be connected between 1 % Section 8 and © NXP B.V. 2007. All rights reserved. ...
Page 11
... RXCMD is not 11b), it must disable the external required when PSW_N is used. This pin is pullup comparators, and also as a power pin for SRP charge BUS pin requires a capacitive load. Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver 15. BUS Table 3 provides the recommended capacitor for BUS supply by setting © ...
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... CHRG_VBUS R UP(VBUS) V BUS comparators R DN(VBUS) DISCHRG_ VBUS 15. Section 15. CC(I/O) Section Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver capacitor (C ) BUS VBUS REG3V3 V BUS R I(idle)(VBUS) 004aaa871 , if not used. The ISP1504x1 contains an 9.3.2. © NXP B.V. 2007. All rights reserved. ...
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... If CS_N/PWRDN is not used, it must be connected to LOW. For more information on using CS_N/PWRDN, see 7.9.18 GND Power and signal ground. To ensure correct operation of the ISP1504x1, GND must be soldered to the cleanest ground available. ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 9.3.1. Section 9.3.3. Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved. ...
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... Receive USB status updates (RXCMDs) For more information on various synchronous mode protocols, see Table 4. Signal name CLOCK DATA[7:0] ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Section Table 4. ULPI signal description Direction on Signal description ISP1504x1 O 60 MHz interface clock: During low-power and serial modes, the clock can be turned off to save power ...
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... An RXCMD may not be sent if the interrupt condition is removed before exiting. For more information on low-power mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 ULPI signal description …continued Direction on Signal description ISP1504x1 O Direction: Controls the direction of data bus DATA[7:0] ...
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... O reserved; the ISP1504x1 will drive this pin to LOW Table Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver 6. To enter 6-pin serial mode, the link sets 7. To enter 3-pin serial mode, the link sets © NXP B.V. 2007. All rights reserved. ...
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... DP and DM when TX_ENABLE is LOW O active HIGH interrupt indication; will be asserted whenever any unmasked interrupt occurs O reserved; the ISP1504x1 will drive these pins to LOW is less than Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved ...
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... PWRDN 3-stated pins summarizes operating states. The values of register settings in Table termination resistors on DP and DM Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver t PWRUP 8. Resistor setting signals are defined as follows: 004aaa733 Table 8 will force © NXP B.V. 2007. All rights reserved. ...
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... Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Internal resistor settings DM_ RPU_DP RPD_DP RPD_ PULL _EN _EN DM_EN DOWN ...
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... ISP1504A1_ISP1504C1_1 Product data sheet TERM OPMODE DP_ SELECT [1:0] PULL DOWN 1b 00b 0b 1b 10b 0b 0b 10b 0b Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver …continued Internal resistor settings DM_ RPU_DP RPD_DP RPD_ PULL _EN _EN DM_EN DOWN ...
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... PLL start-up time CC ). Whenever DIR is asserted, the ISP1504x1 drives the NXT pin to LOW Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver for at least POR(trip) , and then rises above V POR(trip) ...
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... The link may start to detect DIR status level. If DIR is detected LOW for three clock cycles, the link may send a RESET command. 4. The ULPI interface is ready for use. For details on power-up sequence, see ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Figure 6. Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved. ...
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... LOW. The link is expected to issue a RESET command to initialize the ISP1504x1 The power-up sequence is completed and the ULPI bus interface is ready for use. Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 internal clocks stable t startup(PLL) RESET command ...
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... CS_N/PWRDN is not used, it must be tied to LOW. behavior when CS_N/PWRDN is asserted (LOW) and when CS_N/PWRDN is subsequently de-asserted (HIGH). The behavior of de-asserted (HIGH). ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Hi-Z (link must drive) Hi-Z (input) Hi-Z (link must drive) Hi-Z (input) Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver ...
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... OTG Control register power control bits Power source used external power source disabled (PSW_N = HIGH) BUS external power source enabled (PSW_N = LOW) BUS BUS Figure Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver t PWRDN Hi-Z (ignored) Hi-Z (ignored) Hi-Z (ignored) Hi-Z (ignored) Hi-Z (ignored) . BUS fault detector circuits that output a digital fault 10 ...
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... REGW 10 1111b EXTR XX XXXXb REGR Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver 10. Any values other than those in Command description No operation. 00h is the idle value of the data bus. The link must drive NOOP by default. Transmit USB data that does not have a PID, such as chirp and resume signaling ...
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... SE0 squelch squelch FS-J !squelch !squelch and HS_Differential_Receiver_Output FS-K invalid !squelch and !HS_Differential_Receiver_Output SE1 invalid invalid Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Section 9.5.2.1. state, see Section BUS Section 9.5.2.4. Back-to-back RXCMDs turnaround RXCMD RXCMD 9.5.2.2. turnaround 004aaa695 © NXP B.V. 2007. All rights reserved. ...
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... BUS A_VBUS_VLD V V BUS A_VBUS_VLD BUS voltage indicators, as shown in BUS 9.5.2.3. Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Chirp squelch !squelch and HS_Differential_Receiver_Output !squelch and !HS_Differential_Receiver_Output invalid state field in the RXCMD is an encoding of the state are directly taken from ...
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... IND_PASSTHRU bit in the Interface Control register to logic 1. Standard USB Peripheral Controllers: when V BUS start and end of USB peripheral operations. Detection of A_VBUS_VLD and SESS_END thresholds is not needed for standard peripherals. ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 A_VBUS_VLD comparator internal A_VBUS_VLD V BUS FAULT indicator FAULT IND_COMPL ...
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... When the ISP1504x1 has detected a SYNC pattern on the USB bus, it signals When the ISP1504x1 has detected an error while receiving a USB packet, it HostDisconnect is encoded into the RxEvent field of the RXCMD. Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Section “Standard USB Host Controllers” RxError ...
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... XCVRSELECT[1:0] to 00b (high-speed) and OPMODE[1:0] to 10b (chirp). The peripheral immediately follows this with a TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 shows register read and write sequences. The ISP1504x1 supports immediate TXCMD TXCMD (EXTW ...
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... After transmitting the chirp sequence, the host changes OPMODE[1:0] to 00b and begins sending USB packets. For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 . If the peripheral is in low-power mode, it must wake 0 Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver © ...
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... MODE J (01b) SE0 (00b) LINE STATE DP DM Timing is not to scale. Fig 12. USB reset and high-speed detection handshake (chirp) sequence ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 high-speed detection handshake (chirp) peripheral chirp TXCMD (HS) 01 (chirp) squelch peripheral chirp K (10b) (00b) TXCMD ...
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... Table 18 for correct USB system operation. Examples of high-speed Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Figure 13. For details on USB ISP1504x1 ISP1504x1 ISP1504x1 asserts DIR, sends sends causing ...
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... Any subsequent transmission can occur after this time. USB interpacket delay (88 to 192 high-speed bit times) EOP link decision time ( clocks) Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver IDLE (one to two clocks) SYNC D0 ...
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... ISP1504A1_ISP1504C1_1 Product data sheet USB interpacket delay (8 to 192 high-speed bit times) IDLE N turnaround link decision time ( clocks) Figure Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver TXCMD TX start delay (one to two clocks) 16. SYNC D0 D1 004aaa713 © NXP B.V. 2007. All rights reserved. ...
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... PRE ID DP and DM timing is not to scale. illustrates how a host or a hub places a full-speed or low-speed peripheral into Figure 17 timing is not to scale, and does not show all RXCMD Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver D1 D0 IDLE (min SYNC ...
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... RXCMD LINESTATE updates. ISP1504A1_ISP1504C1_1 Product data sheet suspend resume K TXCMD TXCMD (REGW) NOPID LINESTATE J LINESTATE K 00b J illustrates how a host or a hub places a high-speed enabled peripheral into Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver EOP K ... K TXCMD K 10b K SE0 J SE0 J 10b ...
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... The peripheral link sees terminations (TERMSELECT is set to 0b). The host link sets Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver terminations, and enables the 1.5 k terminations (TERMSELECT is set to © NXP B.V. 2007. All rights reserved. ...
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... Product data sheet FS suspend TXCMD TXCMD (REGW) NOPID 01b 00b FS J (01b) LINESTATE K LINESTATE J 01b 00b FS J (01b) Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver resume K HS idle TXCMD ... (REGW) 00b 10b 00b FS K (10b) SQUELCH (00b) ...
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... SE0 of the EOP is completed. This can be achieved by writing XCVRSELECT = 00b and TERMSELECT = 0b after LINESTATE indicates SE0. ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved ...
Page 42
... TXCMD (NOPID) type. The ISP1504x1 does not provide a mechanism to control bit stuffing in individual bytes, but will automatically turn off bit stuffing for EOP when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 TXCMD TXCMD NOPID 00h ...
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... Pull-up and pull-down resistors on DP and DM • ID detector indicates if micro-A or micro-B plug is inserted • Charge and discharge resistors on V The following subsections describe how to use the ISP1504x1 OTG components. ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 00h 00h 80h PID 00h SYNC PID BUS Rev. 01 — ...
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... B-device to discharge V DN(VBUS) BUS is below V BUS B_SESS_END and Figure 22 provide example of 6-pin serial mode and 3-pin serial mode, Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver , V A_VBUS_VLD A_SESS_VLD and V are combined into A_SESS_VLD B_SESS_VLD Section 7.6.2. Changes in comparator values Section 9 ...
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... DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 22. Example of transmit followed by receive in 3-pin serial mode ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 TRANSMIT DATA EOP TRANSMIT DATA SYNC EOP Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver RECEIVE SYNC DATA ...
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... LOW and starts to immediately turn off its output drivers. The link senses the change of DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle, avoiding data bus contention. ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved ...
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... Set (S): The pattern on the data bus is OR-ed with and written to a register. [4] Clear (C): The pattern on the data bus is a mask bit in the mask is set, then the corresponding register bit will be set to zero (cleared). ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Size Address (6 bits) (bits) [1] [2] ...
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... Value Description 15h Product ID High: Upper byte of the NXP product ID number; has a fixed value of 15h Table 25 RESET OPMODE[1: R/W/S/C R/W/S/C Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Table 22. Table 23. Table 24 TERM XCVRSELECT[1:0] SELECT R/W/S/C R/W/S/C ...
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... Reset 0 Access R/W/S/C R/W/S/C ISP1504A1_ISP1504C1_1 Product data sheet 8. Table IND_ reserved COMPL R/W/S/C R/W/S/C Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver provides the bit allocation of the register CLOCK_ reserved 3PIN_ SUSPENDM FSLS_ SERIAL 0 0 R/W/S/C R/W/S/C R/W/S 6PIN_ FSLS_ SERIAL ...
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... VBUS_IND VBUS_EXT Reset 0 Access R/W/S/C R/W/S/C ISP1504A1_ISP1504C1_1 Product data sheet 9.5.2.2. Section Table reserved CHRG_ VBUS R/W/S/C R/W/S/C Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver state in RXCMD. For details, see BUS 9.5.2.2. 29 DISCHRG_ DM_PULL DP_PULL VBUS DOWN DOWN 0 1 R/W/S/C R/W/S/C R/W/S ID_PULL UP 1 ...
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... BUS BUS . BUS . BUS Table 31 shows the bit allocation of the register ID_GND_R R/W/S/C R/W/S/C Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver overcurrent indicator. BUS pulsing of SRP. The link must BUS SESS_ SESS_ VBUS_ END_R VALID_R VALID_R ...
Page 52
... USB Interrupt Status register This register (see ISP1504A1_ISP1504C1_1 Product data sheet Table 33 ID_GND_F R/W/S/C R/W/S/C Table 35) indicates the current value of the interrupt source signal. Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver SESS_ SESS_ VBUS_ END_F VALID_F VALID_F R/W/S/C R/W/S/C R/W/S/C 0 ...
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... Host Disconnect: Reflects the current value of the host disconnect detector ID_GND_L Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD. Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver SESS_ SESS_ VBUS_ END VALID VALID 0 0 ...
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... Scratch: This is an empty register byte for testing purposes. Software can read, write, set and clear this register, and the functionality of the PHY will not be affected reserved R/W/S/C R/W/S/C Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Table 39. This register indicates the LINE STATE1 ...
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... Addresses 40h to FFh are not implemented. Operating on these addresses may result in undefined behavior of the PHY. ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved ...
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... I T ambient temperature amb [1] V must not exceed V . CC(I/O) CC ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Conditions on pins CLOCK, STP, DATA[7:0], RESET_N and CS_N/PWRDN on pins V , FAULT and PSW_N BUS on pin XTAL1 on pin ID on pins DP and DM I < Human Body Model LI ...
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... C to +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions 0 CC(I/ 0 < V < CC(I/O) Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Min Typ 3.0 3.3 1.65 1 235 - [ [ ...
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... V O may increase because of the cross current +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions includes V Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Min Typ Min Typ - - 2.0 - ...
Page 59
... DP 3.6 V pull-down on pins DP and DM GND L excluding the first transition from the idle state includes V pin to GND steady-state drive steady-state drive Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Min Typ = 0.0 0.18 L 2.8 3.2 1.3 - 3.0 - 1425 1500 100 - ...
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... CC(I/O) amb Conditions connect to pin REG3V3 ID_PULLUP is logic +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions SUSPENDM is logic 1 Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Min Typ 4.4 - 0.8 1 0.2 0.5 281 680 656 ...
Page 61
... REG1V8 and REG3V3 ISP1504A1ET ISP1504C1ET f = 19.2 MHz i(XTAL1 MHz i(XTAL1) only for square wave input only for square wave input only for square wave input Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Min Typ 0 200 - - 650 ...
Page 62
... C to +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions 30 pF load; see Figure 28 line impedance 50 line impedance 50 Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Min Typ 5 4 ...
Page 63
... TX_ENABLE to DP, DM; see Figure 25 TX_ENABLE to DP, DM; see Figure 25 TX_ENABLE to DP, DM; see Figure 25 DP RX_RCV, RX_DP and RX_DM; see Figure 26 DP RX_RCV, RX_DP and RX_DM; see Figure 26 Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Min Typ 500 - 500 - ...
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... Fig 24. Timing of TX_DAT and TX_SE0 to DP and DM differential data lines 0 PHZ t PLZ V 0 logic output 004aaa574 Fig 26. Timing of DP and DM to RX_RCV, RX_DP and Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver …continued Min Typ - - - - 0 PLH(drv) differential V CRS data lines 2 CRS 0 ...
Page 65
... ISP1504A1_ISP1504C1_1 Product data sheet CLOCK t t su(STP) h(STP) (STP su(DATA) h(DATA) (8-BIT) (8-BIT) CLOCK DATA[7:0] link releases data bus Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver t , d(DIR) t d(NXT d(DIR d(DATA) d(NXT) turnaround cycle t d(busturn-DV) DRIVE 3-STATE ...
Page 66
... F and 6 parallel IP4359CX4/LF 4.7 k (recommended) supply 19.2 MHz 26 MHz 100 pF Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver Comment - - - - - Wafer-Level Chip-Scale Package (WLCSP); ESD IEC 61000-4-2 level contact air discharge compliant protection - - - used to avoid fl ...
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V BUS USB D+ STANDARD-B 4 GND RECEPTACLE A1 IP4359CX4/ ESD C VBUS C bypass Fig 29. Using the ISP1504x1 with a standard USB Peripheral Controller; external crystal V V CC(I/ ...
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V IN FAULT V BUS R pullup SWITCH ON OUT 1 V BUS USB MICRO- RECEPTACLE 5 GND A1 IP4359CX4/ ESD C VBUS (1) Can be a square wave clock of ...
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V IN FAULT V BUS R pullup SWITCH ON OUT 1 V BUS USB D+ STANDARD-A 4 GND RECEPTACLE IP4359CX4/LF D ESD C VBUS Fig 31. Using the ISP1504x1 with a standard USB Host Controller; external ...
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... 3.6 3.6 0.5 2.5 2.5 0.15 3.4 3.4 REFERENCES JEDEC JEITA - - - - - - Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver detail 0.05 0.08 0.1 EUROPEAN PROJECTION SOT912-1 y ISSUE DATE 05-08-09 05-09-01 © NXP B.V. 2007. All rights reserved ...
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... Solder bath specifications, including temperature and impurities ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver © NXP B.V. 2007. All rights reserved ...
Page 72
... Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 and 60 SnPb eutectic process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < ...
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... Low-Speed Machine Model Non-Return-to-Zero Inverted On-The-Go [1] Physical Layer Packet Identifier Phase-Locked Loop Power-On Reset Receive Command Single-Ended Zero Rev. 01 — 6 August 2007 ISP1504A1; ISP1504C1 ULPI HS USB OTG transceiver peak temperature time 001aac844 © NXP B.V. 2007. All rights reserved ...
Page 74
... Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components (JESD22-C101-C) 20. Revision history Table 62. Revision history Document ID Release date Data sheet status ISP1504A1_ISP1504C1_1 20070806 ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Abbreviations …continued Description Start-Of-Frame Session Request Protocol Synchronous Transistor-Transistor Logic Transmit Command Universal Serial Bus USB Implementers Forum UTMI+ Low Pin Interface USB 2 ...
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... Contact information For additional information, please visit: For sales office addresses, send an email to: ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 [3] Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. ...
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... Table 30. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Table 31. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit allocation . . . . . . . . . . . . . . . . . . . 51 Table 32. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description ...
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... Table 58. Recommended bill of materials . . . . . . . . . . . .66 Table 59. SnPb eutectic process (from J-STD-020C .72 Table 60. Lead-free process (from J-STD-020C .72 Table 61. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 62. Revision history . . . . . . . . . . . . . . . . . . . . . . . .74 ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver continued >> © NXP B.V. 2007. All rights reserved ...
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... Fig 31. Using the ISP1504x1 with a standard USB Host Controller; external 5 V source with built-in FAULT and external crystal . . . . . . . . . . . . . . . . .69 Fig 32. Package outline SOT912-1 (TFBGA36 .70 ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 Fig 33. Temperature profiles for large and small components Rev. 01 — 6 August 2007 ULPI HS USB OTG transceiver continued >> ...
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... CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9.17 CS_N/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9.18 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Modes of operation . . . . . . . . . . . . . . . . . . . . . 14 8.1 ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.1 Synchronous mode 8.1.2 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 15 ISP1504A1_ISP1504C1_1 Product data sheet ISP1504A1; ISP1504C1 8.1.3 6-pin full-speed or low-speed serial mode . . . 16 8.1.4 3-pin full-speed or low-speed serial mode . . . 16 8.1.5 Power-down mode . . . . . . . . . . . . . . . . . . . . . 17 8.2 USB state transitions . . . . . . . . . . . . . . . . . . . 18 9 Protocol description . . . . . . . . . . . . . . . . . . . . 21 9.1 ULPI references . . . . . . . . . . . . . . . . . . . . . . . 21 9.2 Power-On Reset (POR ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: ISP1504A1_ISP1504C1_1 All rights reserved. Date of release: 6 August 2007 ...