isp1520 NXP Semiconductors, isp1520 Datasheet - Page 15

• Manufacturer Part Number: isp1520
• Description: Hi-speed Universal Serial Bus Hub Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
ISP1520_4
Product data sheet
8.2.1.2 Data transfer
8.2.1.3 I
8.2.2 Architecture of configurable hub descriptors
The master initiates each data transfer using a START condition and terminates it by
generating a STOP condition. To facilitate the next byte transfer, each byte of data must be
acknowledged by the receiver. The acknowledgment is done by pulling the SDA line LOW
on the ninth bit of the data. An extra clock pulse must be generated by the master to
accommodate this bit.
For details on the operation of the bus, refer to The I
The address of the ISP1520 is given in
Table 10.
The configurable hub descriptors can be masked in the internal ROM memory; see
Figure
microcontroller. The ISP1520 implements both the master and slave I
The information from the external EEPROM or the microcontroller is transferred into the
internal RAM during the power-on reset. A signature word is used to identify correct
descriptors. If the signature matches, the content of the RAM is chosen instead of the
ROM.
2
Bit
Value
Fig 7. Configurable hub descriptors
C-bus address
7. These descriptors can also be supplied from an external EEPROM or a
The I
I
MSB
A7
0
2
C-bus slave address
2
C-bus cannot be shared between the EEPROM and the external microcontroller.
HUB CORE
Slave address
A6
0
Rev. 04 — 28 April 2006
A5
1
DESCRIPTOR
GENERATOR
INTERFACE
Table
MICROCONTROLLER
A4
1
10.
A3
0
MUX
2
signature
C-bus specification .
match
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Hi-Speed USB hub controller
A2
1
I
2
SERIAL EEPROM
C-BUS INTERFACE
MASTER/SLAVE
(256 B)
(256 B)
ROM
RAM
2
C-bus controllers.
LSB
A1
0
I
2
ISP1520
C-bus
mld711
Write
0
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