isp1760 NXP Semiconductors, isp1760 Datasheet - Page 104

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
27. Contents
1
2
3
3.1
4
5
6
6.1
6.2
7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
7.6
7.7
7.8
7.9
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
9397 750 13257
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . 12
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Examples of a multitude of possible
applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
ISP1760 internal architecture: Advanced Philips
Slave Host Controller and hub . . . . . . . . . . . . 12
Host Controller buffer memory block . . . . . . . 13
General considerations. . . . . . . . . . . . . . . . . . 13
Structure of the ISP1760 Host Controller
memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Accessing the ISP1760 Host Controller memory:
PIO and DMA . . . . . . . . . . . . . . . . . . . . . . . . . 16
PIO mode access—memory read cycle . . . . . 17
PIO mode access—memory write cycle. . . . . 17
PIO mode access—register read cycle . . . . . 18
PIO mode access—register write cycle . . . . . 18
DMA—read and write operations . . . . . . . . . . 18
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Phase-Locked Loop (PLL) clock multiplier . . . 21
Power management . . . . . . . . . . . . . . . . . . . . 22
Overcurrent detection . . . . . . . . . . . . . . . . . . . 23
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-on reset (POR) . . . . . . . . . . . . . . . . . . 25
EHCI capability registers . . . . . . . . . . . . . . . . 28
CAPLENGTH register (R: 0000h). . . . . . . . . . 28
HCIVERSION register (R: 0002h) . . . . . . . . . 28
HCSPARAMS register (R: 0004h) . . . . . . . . . 28
HCCPARAMS register (R: 0008h) . . . . . . . . . 29
EHCI operational registers . . . . . . . . . . . . . . . 30
USBCMD register (R/W: 0020h). . . . . . . . . . . 30
USBSTS register (R/W: 0024h) . . . . . . . . . . . 31
USBINTR register (R/W: 0028h). . . . . . . . . . . 32
FRINDEX register (R/W: 002Ch) . . . . . . . . . . 33
CTRLDSSEGMENT register (R/W: 0030h) . . 34
CONFIGFLAG register (R/W: 0060h) . . . . . . . 34
PORTSC1 register (R/W: 0064h) . . . . . . . . . . 35
ISO PTD Done Map register (R: 0130h). . . . . 36
ISO PTD Skip Map register (R/W: 0134h) . . . 37
Rev. 01 — 8 November 2004
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
8.2.15
8.2.16
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
9
9.1
9.2
9.3
9.4
9.5
9.6
10
11
Philips Transfer Descriptor. . . . . . . . . . . . . . . 55
Power consumption . . . . . . . . . . . . . . . . . . . . 82
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 83
ISO PTD Last PTD register (R/W: 0138h) . . . 37
INT PTD Done Map register (R: 0140h). . . . . 37
INT PTD Skip Map register (R/W: 0144h) . . . 38
INT PTD Last PTD register (R/W: 0148h) . . . 38
ATL PTD Done Map register (R: 0150h) . . . . 38
ATL PTD Skip Map register (R/W: 0154h) . . . 38
ATL PTD Last PTD register (R/W: 0158h) . . . 39
Configuration registers . . . . . . . . . . . . . . . . . . 39
HW Mode Control register (R/W: 0300h) . . . . 39
Chip ID register (R: 0304h) . . . . . . . . . . . . . . 41
Scratch register (R/W: 0308h) . . . . . . . . . . . . 41
SW Reset register (R/W: 030Ch) . . . . . . . . . . 41
DMA Configuration register (R/W: 0330h) . . . 42
Buffer Status register (R/W: 0334h) . . . . . . . . 43
ATL Done Timeout register (R/W: 0338h) . . . 44
Memory register (R/W: 033Ch) . . . . . . . . . . . 44
Edge Interrupt Count register (R/W: 0340h) . 45
DMA Start Address register (W: 0344h) . . . . 46
Power Down Control register (R/W: 0354h) . . 46
Port 1 Control register (R/W: 0374h) . . . . . . . 48
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt register (R/W: 0310h) . . . . . . . . . . . 50
Interrupt Enable register (R/W: 0314h) . . . . . 51
ISO IRQ Mask OR register (R/W: 0318h) . . . 53
INT IRQ Mask OR register (R/W: 031Ch) . . . 53
ATL IRQ Mask OR register (R/W: 0320h) . . . 53
ISO IRQ Mask AND register (R/W: 0324h) . . 54
INT IRQ Mask AND register (R/W: 0328h) . . 54
ATL IRQ Mask AND register (R/W: 032Ch) . . 54
High-speed bulk IN and OUT, Queue Head
Asynchronous (QHA) (patent-pending) . . . . . 58
High-speed isochronous IN and OUT,
isochronous Transfer Descriptor (iTD)
(patent-pending). . . . . . . . . . . . . . . . . . . . . . . 62
High-speed interrupt IN and OUT, Queue Head
Periodic (QHP) (patent-pending) . . . . . . . . . . 66
Start and complete split for bulk, Queue Head
Asynchronous Start Split and Start Complete
(QHA-SS/SC) (patent-pending) . . . . . . . . . . . 70
Start and complete split for isochronous, Split
isochronous Transfer Descriptor (SiTD)
(patent-pending). . . . . . . . . . . . . . . . . . . . . . . 74
Start and complete split for interrupt
(patent-pending). . . . . . . . . . . . . . . . . . . . . . . 78
Embedded Hi-Speed USB host controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1760
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