isp1760 NXP Semiconductors, isp1760 Datasheet - Page 32

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 14:
[1]
Table 16:
9397 750 13257
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
USBSTS register: bit allocation
USBINTR register: bit allocation
8.2.3 USBINTR register (R/W: 0028h)
R/W
R/W
R/W
R/W
R/W
31
23
15
31
0
0
0
7
0
0
Table 15:
[1]
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the
corresponding interrupt to the software. When a bit is set and the corresponding interrupt
is active, an interrupt is generated to the host. Interrupt sources that are disabled in this
register still appear in USBSTS to allow the software to poll for events. The USBINTR
register bit allocation is given in
Bit
31 to 4 -
3
2
1 to 0
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0 .
R/W
R/W
R/W
R/W
R/W
30
22
14
30
0
0
0
6
0
0
Symbol Description
FLR
PCD
-
reserved
USBSTS register: bit description
reserved; write logic 0
Frame List Rollover: The Host Controller sets this bit to logic 1 when the
Frame List Index rolls over from its maximum value to zero.
Port Change Detect: The Host Controller sets this bit to logic 1 when any port,
where the PO bit is cleared, has a change to a one or a FPR bit changes to a
one as a result of a J-K transition detected on a suspended port.
reserved
[1]
R/W
R/W
R/W
R/W
R/W
29
21
13
29
0
0
0
5
0
0
Rev. 01 — 8 November 2004
[1]
R/W
R/W
R/W
R/W
R/W
Table
28
20
12
28
0
0
1
4
0
0
reserved
reserved
reserved
reserved
16.
[1]
[1]
[1]
[1]
R/W
R/W
R/W
FLR
R/W
R/W
27
19
11
27
0
0
0
3
0
0
Embedded Hi-Speed USB host controller
PCD
R/W
R/W
R/W
R/W
R/W
26
18
10
26
0
0
0
2
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
R/W
R/W
R/W
R/W
R/W
25
17
25
0
0
9
0
1
0
0
reserved
ISP1760
[1]
R/W
R/W
R/W
R/W
R/W
32 of 105
24
16
24
0
0
8
0
0
0
0