isp1760 NXP Semiconductors, isp1760 Datasheet - Page 33

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
[1]
Table 18:
9397 750 13257
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
FRINDEX register: bit allocation
8.2.4 FRINDEX register (R/W: 002Ch)
R/W
R/W
R/W
R/W
23
15
31
0
0
7
0
0
Table 17:
[1]
The Frame Index (FRINDEX) register is used by the Host Controller to index into the
periodic frame list. The register updates every 125 s (once each microframe). Bits n to 3
are used to select a particular entry in the Periodic Frame List during periodic schedule
execution. The number of bits used for the index depends on the size of the frame list as
set by the system software in the FLS (Frame List Size) field of the USBCMD register.
This register must be written as a Double Word. A Word-only write (16-bit mode) produces
undefined results. This register cannot be written unless the Host Controller is in the
halted state as indicated by the HCH (HCHalted) bit. A write to this register while the RS
(Run/Stop) bit is set produces undefined results. Writes to this register also affect the SOF
value. The bit allocation is given in
Bit
31 to 4
3
2
1 to 0
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0 .
R/W
R/W
R/W
R/W
22
14
30
0
0
6
0
0
reserved
Symbol
-
FLRE
PCIE
-
USBINTR register: bit description
[1]
R/W
R/W
R/W
R/W
21
13
29
0
0
5
0
0
Rev. 01 — 8 November 2004
Description
reserved
Frame List Rollover Enable: When this bit is set and the FLR bit in the
USBSTS register is set, the Host Controller issues an interrupt. The
interrupt is acknowledged by software clearing bit FLR.
Port Change Interrupt Enable: When this bit is set and the PCD bit in the
USBSTS register is set, the Host Controller issues an interrupt. The
interrupt is acknowledged by software clearing bit PCD.
reserved
R/W
R/W
R/W
R/W
20
12
28
0
0
4
0
0
[1]
reserved
reserved
reserved
Table
18.
[1]
[1]
[1]
FLRE
R/W
R/W
R/W
R/W
19
11
27
0
0
3
0
0
Embedded Hi-Speed USB host controller
PCIE
R/W
R/W
R/W
R/W
18
10
26
0
0
2
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
R/W
R/W
R/W
R/W
17
25
0
9
0
1
0
0
reserved
ISP1760
[1]
R/W
R/W
R/W
R/W
33 of 105
16
24
0
8
0
0
0
0