isp1760 NXP Semiconductors, isp1760 Datasheet - Page 47

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 50:
[1]
9397 750 13257
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Power Down Control register: bit allocation
R/W
R/W
R/W
R/W
31
23
15
0
1
0
7
1
reserved
Table 51:
Bit
31 to 16
15 to 13
12
11
reserved
[1]
[1]
R/W
R/W
R/W
R/W
30
22
14
0
1
0
6
0
Symbol
CLK_OFF
_COUNTER
[15:0]
-
PORT3_
PD
PORT2_
PD
Power Down Control register: bit description
[1]
BIASEN
R/W
R/W
R/W
R/W
29
21
13
0
1
0
5
1
Rev. 01 — 8 November 2004
Description
Clock Off Counter: Determines the wake-up status duration after any
wake-up event before the ISP1760 goes back into suspend mode. This
timeout is applicable only if, during the given interval, the Host
Controller is not programmed back to the normal functionality.
03E8h — The default value. It determines the default wake-up interval
of 10 ms. A value of zero implies that the Host Controller never wakes
up on any of the events. This may be useful when using the ISP1760 as
a peripheral to save power by permanently programming the Host
Controller in suspend.
FFFFh — The maximum value. It determines a maximum wake-up time
of 500 ms.
The setting of this register is based on the 100 kHz
frequency. It is a multiple of 10 s period. In 16-bit mode, a write
operation to these bits with any value will determine a fixed wake-up
time of 50 ms.
reserved
Port 3 Pull-Down: Controls port 3 pull-down resistors.
0 — Port 3 pull-down resistors are connected in suspend
1 — Port 3 pull-down resistors are not connected in suspend.
Port 2 Pull-Down: Controls port 2 pull-down resistors.
0 — Port 2 internal pull-down resistors are connected in suspend
1 — Port 2 internal pull-down resistors are not connected in suspend.
CLK_OFF_COUNTER[15:8]
CLK_OFF_COUNTER[7:0]
VREG_ON
PORT3_
R/W
R/W
R/W
R/W
PD
28
20
12
0
0
1
4
0
OC3_PWR
PORT2_
R/W
R/W
R/W
R/W
PD
27
19
11
0
1
1
3
0
Embedded Hi-Speed USB host controller
VBATDET_
OC2_PWR
PWR
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
OC1_PWR
R/W
R/W
R/W
R/W
25
17
1
0
9
1
1
0
reserved
ISP1760
40 % LazyClock
HC_CLK_
[1]
R/W
R/W
R/W
R/W
47 of 105
EN
24
16
1
0
8
1
0
0