lan83c175 Standard Microsystems Corp., lan83c175 Datasheet
lan83c175
Related parts for lan83c175
lan83c175 Summary of contents
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... LAN83C175 - EPIC/C Ethernet CARDBUS Integrated Controller With Modem Support IEEE 802.3 Compliant 10/100 Mb/s Ethernet Controller Fully Compliant Glueless Integrated CardBus Interface Secondary 8 Bit interface to Support Multi- function CardBus Adpaters Including LAN / Rockwell or Lucent Modem Combinations Supports 3. Modem and Physical Layer Interface ...
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FEATURES ........................................................................................................................................1 GENERAL DESCRIPTION .................................................................................................................3 PIN CONFIGURATION.......................................................................................................................5 DESCRIPTION OF PIN FUNCTIONS .................................................................................................6 FUNCTIONAL DESCRIPTION............................................................................................................9 DMA OPERATION............................................................................................................................11 TRANSMIT DMA ..............................................................................................................................11 RECEIVE DMA.................................................................................................................................17 TRANSMIT/RECEIVE ARBITRATION FOR C BIG/LITTLE ENDIAN SUPPORT.......................................................................................................25 MAC O ................................................................................................................................28 PERATION MAC R ..................................................................................................................................28 ECEIVER MAC TRANSMITTER........................................................................................................................30 MII MANAGEMENT ...
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... Lookahead Buffering Mode, which eliminates the need to re-copy the data from one host memory location to another. The LAN83C175 also includes a secondary 802.3 Media general purpose 8-bit interface with appropriate registers, address lines and control lines. This secondary interface provides all of the signals required to implement a secondary function on a CardBus adpater ...
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... Epic/C MPWRDWN MRESET_N Cardbus Cardbus Interface Physical Layer Interface PHY FIGURE 1 - LAN83C175 SYSTEM DIAGRAM RDYM AUDIOIN RINGIN RINGOUT IREQM MCS_N MA(x:0) MA(15:0) MD(7:0) WR_N RD_N RAMCS_N 4 RDYM AUDIO RINGIN RINGOUT PWRDWN HINT ~RESET ~HCS HA(x:0) HD(7:0) ~HWT ~HRD Modem ADDR(15:0) DATA(7:0) RAMWE_N RAMOE_N RAMCS_N RAM ...
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... N/C 3 COL 4 TX_CLK 5 FETPWR_PHY 6 GND 7 X20 8 VDD 9 3.3 VDD 10 3.3 BIAS 11 ZENER 12 GND 13 CLK25IN 14 nPHY_PWRDWN 15 GND 16 694nEN 17 VDD 18 PHY 694nLNK 19 TEST 20 LAN83C175 GPIO1 21 GPIO2 22 N/C 23 VDD 24 3.3 GND 25 GND 26 nCINT 27 nRST 28 208 Pin TQFP GND 29 CBCLK 30 VDD 31 3.3 nCCLKRUN 32 nCGNT 33 GND 34 nCREQ 35 VDD 36 3.3 N/C 37 GND ...
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DESCRIPTION OF PIN FUNCTIONS TQFP PIN NO. NAME 30 CBCLK 28 nRST 39,40,42,44,45,47,48,58 CAD[31:0] , 61-63,65,66,68,69,71, 91,92,94,95,97,100-102, 108,111,113,114,117, 118,120,121 59,72,88,107 nCBE[3:0] 87 CPAR 74 nCFRAME 75 nCIRDY 78 nCTRDY 81 nCSTOP 82 nCBLOCK 79 nCDEVSEL 35 nCREQ 33 nCGNT 84 ...
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TQFP PIN NO. NAME 206 RX_CLK 184 CRS 189,188,186,185 RXD[3:0] 4 COL 204 RX_DV 203 RX_ER 200 MCLK 202 MDATA 19 694nLNK 17 694nEN 14 CLK25IN 21 GPIO1 22 GPIO2 20 TEST 8 X20 11 BIAS 12 ZENER 199 PHYRST ...
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TQFP PIN NO. NAME 169 AUDIOIN 56 AUDIOOUT 9,10,24,31,36,41,46, VDD 51,53,57,64,73,80,86, 90,96,103,105,109, 115,122,125,146,174, 205 1,18,187,191,208 VDD 140,142,156,157,171 VDD 2,7,13,16,25,26,29, GND 34,38,43,49,52,54,60, 67,70,76,83,89,93,99, 104,106,112,116,119, 124,126,132,135,138, 144,155,158,163,167, 190,194,197,201,207 3,23,37,55,77,98,110, N/C 123,127,149,154,175, 182,183 I/O DESCRIPTION I Audio input to the chip TTL4 O ...
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... The LAN83C175 is a two channel bus master (one for transmit, one for receive) capable of transferring data at the maximum CardBus transfer rate of 132 Mbps. Buffer format in host memory is controlled by an independent linked list structure for each channel. ...
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Flash EEPROM for CIS and config. 32 bit Cardbus PCI RECEIVE DMA BUS MASTER SLAVE PCI INTERFACE Config and Status PCI CLOCK MULT. TRANSMIT DMA SYS CLOCK FIGURE 2 - EPIC/C BLOCK DIAGRAM Modem Chipset Local Bus INTERNAL Receive CSMA/CD ...
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DMA OPERATION The software driver controls the transmit and receive DMA controllers through the I/O control registers and through "buffer descriptors" in host memory. There is an independent chain (linked list) of descriptors for each DMA. descriptor may point to ...
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... DMA will read the from the location in host memory pointed to by its Current Descriptor Address register. ownership bit in the descriptor is equal to 1 then the LAN83C175 will accept the descriptor and update its Current Descriptor Address register with the value in the Next Descriptor Address field. ...
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... If the ownership bit is 0, then the LAN83C175 will clear TXQUEUED and set the transmit queue empty interrupt. If the ownership bit is 1, then the LAN83C175 will begin copying the next frame into the local transmit RAM. The DMA will continue copying ...
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... LAN83C175 will post the status into the first descriptor and immediately initiate the second transmission. If the transmission completes before the copy is done, the LAN83C175 will pause between fragments to post the status and then resume the copy. If the early transmit threshold has ...
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FRAME 1 STATUS TX LENGTH/STATUS BUFFER ADDRESS CONTROL/BUF LENGTH NEXT DESCR. ADDRESS TX LENGTH/STATUS BUFFER ADDRESS CONTROL/BUF LENGTH NEXT DESCR. ADDRESS TX LENGTH/STATUS BUFFER ADDRESS CONTROL/BUF LENGTH NEXT DESCR. ADDRESS FRAGLIST - 1 FIGURE 3 - TRANSMIT BUFFER STRUCTURE FRAME ...
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... TXQUEUED bit should be set. TXQUEUED can be written regardless of completion status and will ensure that the latest frame is transmitted. If the LAN83C175 reaches the end of the transmit queue before the new frame has been added, a transmit chain complete interrupt is generated for the ...
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Maximum Transmit Size and Burst Rate The transmit DMA supports frame sizes Kbytes. The maximum size for a single data buffer (fragment) is also 64 Kbytes. The transmit DMA will run at the maximum CardBus data rate ...
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DWORD 0 - Status Bit Number and Description 31 through 16 - RECEIVE FRAME LENGTH: Number of bytes in the received frame OWNER: Descriptor ownership bit - set to “0” when the host owns the descriptor, set to ...
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... RXQUEUED bit will be cleared (and the receive queue empty (RQE) interrupt set) and the Current Descriptor Address register will not be changed. If the ownership bit is equal to 1, the LAN83C175 will accept the descriptor and update its Current Descriptor Address register with the value in the Next Descriptor Address field ...
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... Receive Lookahead Method When this buffering LAN83C175 first copies only the header of a frame into host memory, and then waits for a queue from the software driver before copying the rest of the frame. The software usually specifies the final destination of the frame data with a fragment list ...
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... RXQUEUED to discard the frame, as described above. However, the next descriptor in the receive descriptor list must have the ownership bit cleared (host still owns descriptor). This allows the LAN83C175 to update the PRSTAT register without starting to copy the following frame. The software driver must poll the RQE (receive queue empty) interrupt to determine when the status is available ...
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After the header descriptor is queued, the software may set RXQUEUED again to guarantee that the header descriptor is recognized. When the DMA is finished copying the first frame, it will ...
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READ DESCRIPTOR GO TO NEXT FRAME COPY HEADER POST STATUS TRUE NEXTFRAME READ DESCRIPTOR COPY FRAME POST STATUS RDMA STOPPED (RXQUEUED=0) FALSE NEXTFRAME FIGURE 4 - RECEIVE LOCKAHEAD BUFFERING FLOW RESET WAIT RXQUEUED SET HEADER BIT SET OWNER HOST/CLEAR RXQUEUED ...
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Stopping the Receive DMA The receive DMA may be halted by setting the STOP_RDMA bit in the command register. Setting this bit forces RXQUEUED to 0. The CSMA/CD receiver should also be taken off-line to prevent it from continuing to ...
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... When programmed into Big Endian mode, the LAN83C175 will automatically swap the data (Note: bytes internally descriptor tables or fragment lists. This allows ...
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... Big Endian machine. CardBus When reading or writing Ethernet packet data, the LAN83C175 will not perform any byte to the swapping internally because the data on the The CardBus bus will already be in the correct order. ...
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Control Register dword transfer Descriptor/Fragment list dword transfer FIGURE 5 - LITTLE ENDIAN/BIG ENDIAN BYTE TRANSFER The number in the ...
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... The CRS and COL signals provide carrier sense and collision detect respectively. In parallel mode, the physical layer device transfers data to the LAN83C175 four bits at a time on the RXD[3-0] data bus. transferred synchronously to the falling edge of RXC. The signal Receive Data Valid (RX_DV) informs the MAC of the RXD bus status ...
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Computation stops after the reception of the last whole byte following loss of carrier in serial mode or the transition of RX_DV from active to inactive in parallel mode. The final value of the CRC must be "C704DD7B" for the ...
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... The missed packet counter is 8 bits wide and generates an interrupt when it reaches a count of 192. MAC TRANSMITTER The LAN83C175 capable of generating network data at rates of When this 10 and 100 Mbps. implementations of 10 Mbps physical layer devices, and the 802.3u Media Independent Interface (MII) for 10 and 100 Mbps ...
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Optional operating modes can be selected by programming the transmit configuration register. Preamble Generation At the beginning of each packet, the transmitter generates 56 bits of preamble (an alternating '1010' pattern). Following the preamble, a ...
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... LAN83C175 supports specification for the MII Serial Management Interface. EEPROM INTERFACE The LAN83C175 has a 8-bit parallel interface to an external EEPROM. The parallel EEPROM contains the LAN Address for the adapter and a several bytes of configuration information. The LAN address and configuration information is ...
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EEPROM Format The format of the EEPROM is shown in the following Table. Note that this denotes only the first 7 Dwords of the EEPROM. DWORD BITS 23-16 0 31- 23-16 1 31-24 2 ...
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... All other functions are disabled (attempting any other operation will cause unpredictable behavior). The power down bit must only be set when the LAN83C175 is in its idle state. When the nRST pin is asserted, the LAN83C175 will automatically enter power down mode after recalling the contents of the EEPROM ...
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... When the expansion LAN83C175 will always return all four bytes in the dword being accessed, regardless of which byte enables are active. The LAN83C175 will write to the flash ROM on a byte basis, as decoded by the byte enables. 35 When registers Access to the control ROM ...
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ROM DECODE MEMORY ENABLE MAP ENABLE After reset, the ROM will be disabled and the ROM base address will be ...
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... Used during initialization only (illegal to access when not idle). 2 Legal to access during transmit underrun only. 3 Legal to access only when frame is discarded after header copy and INTSTAT.RSV Legal to access only in test mode. of the LAN83C175 control registers. registers are dword accessible only LAN0 80 PRFDAR ...
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... INTERRUPT STATUS Reset Value: 01001100000000000000000 Bits in this register are set internally by the LAN83C175. Bits are cleared by writing their respective locations. Writing bit has no effect (in register test mode writing 0 sets the bit). 31 through 28 - Unused ...
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DPE: CardBus data parity error - set when a data parity error occurs on the CardBus bus while EPIC/C is bus master. This interrupt will only be set when the Parity Error Response bit in the configuration space ...
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TXUGO bit Transmit queue empty - set when NIC reads a transmit descriptor that is still owned by the host. This interrupt is cleared automatically when the TXQUEUED ...
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... LAN83C175 interrupt line. When one of the Full) interrupt status bits and its corresponding mask 128 Bytes bit are both set, the LAN83C175 will drive the (Full) nINTA pin low. interrupts (except software interrupt SOFT RESET: Setting this bit resets the LAN83C175 to its initialization state ...
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... LAN83C175 from the modem, if statusreg_en is inactive. It must be set able to write to and read from the function registers for both the ethernet and modem functions ...
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EEPROM CONTROL Reset Value: xxx0000 6 - EEPROM SIZE: This read only bit indicates the size of the external serial EEPROM (1 = 16x16 or 64x16 128x16 or 256x16). The size is selected by an external ...
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RECEIVE FIFO Reset Value: xxxxxxxxxxxxxxxx 31 through 16 - Unused. 15 through 0 - The receive fifo can be read and written through this I/O port (for test purposes only). The upper and lower 16 bits of each ...
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... LINK STATUS: This bit is read only and returns the value of the 694LNK pin on the LAN83C175 ENABLE 694: When set, the EN694 pin of the LAN83C175 is driven to a logic one. When clear, the EN694 pin is driven low SERIAL MODE ENABLE: When set, the MII interface functions serially interface ...
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Where each N is one nibble, will be mapped to the LAN address registers as follows: LAN0 [15-12 LAN0 [11- LAN0 [7- LAN0 [3- LAN1 [15-12 LAN1 [11- ...
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BOARD ID/CHECKSUM Power Up Reset XXXXXXXXXXXXXXXX These registers hold the board ID and the checksum for the adapter. They are recalled from EEPROM after reset. 31 through 16: Unused. 15 through 8 - BOARD ID: Used as the ...
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The receive status register reports the status of the most-recently received packet. reports receive errors and address recognition type. All bits are cleared at the start of reception except for receiver disabled. contents of the lower order bits in this ...
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D2 D1 Mode 0 0 Normal operation Internal loopback. transmitted are internally looped back to the receiver without transmission to the MII External loopback. Turns on the external loopback mode to signal the PHY to loop ...
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TRANSMIT PACKET ADDRESS Reset Value: 000000000 This register contains the transmit MTU’s pointer to the starting address of the current frame in the local transmit ram. The register contains the dword address and is write only. Reads to ...
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CardBus RECEIVE FRAGMENT LIST ADDRESS Reset Value: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00 This register contains the current fragment list address the location in host memory of the next fragment list entry that the receive DMA will read. The two lsb’s ...
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CardBus RECEIVE RAM PACKET ADDRESS Reset Value: The PRLPAR register will always point to the starting address of the internal receive memory after reset. address will be determined by the memory size jumper settings: SIZE RESET VALUE 128K ...
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... Address CardBus RECEIVE COPY THRESHOLD Reset Value: 11111111XX This register is programmed with the CardBus receive copy threshold for the LAN83C175. An early receive warning interrupt will be generated for each frame after the number of specified in this register have been copied into the receive data buffers in host memory. Bits 1 and 0 are ignored, so the granularity of threshold is four bytes ...
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BC - PREEMPTIVE INTERRUPT Reset Value: 00000000000 This register is used to set the preemptive interrupt value, the number of bytes before the end of a packet that a packet received interrupt will be issued. The register is writable but ...
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... RAM. Bits 1 and 0 are ignored, so the granularity of the threshold is four bytes. Data written into this register will automatically be stored in the early transmit count register at the same time. The register should only be written at initialization time. 31 through 11: Unused LAN83C175. ...
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THRESHOLD 1 and 0: Not writable - return unknown data. Note: There are a set of configuration registers for both the Ethernet and modem function CardBus EARLY TRANSMIT COUNT Reset Value: xxxxxxxxx This counter contains ...
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UNDERRUN: This bit is set when the transmit DMA is unable to supply the transmitter enough data to maintain frame transmission CARRIER SENSE LOST: This bit is set if the carrier is lost during packet transmission. ...
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FO - FEVTR Reset Value: 0xxxxxxxxxxxxxxx This bit is used for CardBus purposes FEVTR: This function event register bit is a register for holding interrupts in the CardBus environment. 14 through 0 - unused FEVTRMSKR Reset ...
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... CardBus Configuration Registers The following table shows the address mapping for the LAN83C175 configuration registers. Table 3 - CardBus Configuration Registers 31 00 Device ID 04 Status 08 0C Unused Subsystem Max Lat Note: All unused and reserved registers return zeroes when read. Writes to unused and reserved registers are ignored ...
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... LAN83C175 always asserts DEVSEL with fast timing (zero wait states). vs DATA PARITY DETECTED: This bit is set whenever the following three conditions are met: 1) the LAN83C175 is acting as bus master on the CardBus bus; 2) the LAN83C175 asserts nPERR or observes nPERR asserted; 3) the Parity Error Response bit is set. ...
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... WAIT CYCLE CONTROL: This bit is not implemented because the LAN83C175 does not do address/data stepping (always returns 0 PARITY ERROR RESPONSE: When this bit is set the LAN83C175 will respond to parity errors. When cleared, the LAN83C175 will ignore parity errors. 5 through 3 - VGA PALETTE SNOOP, ...
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... Reset Value: unknown; written during EEPROM recall This read only register is used to uniquely identify the add-in board or subsystem on which LAN83C175 resides. The value is recalled from EEPROM after power-up reset. 31 through 16 - SUBSYSTEM ID: This field is vendor specific and may be assigned freely. Bit 31 is hardwired to 0. ...
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... LAN83C175's interrupt pin is connected to. Values in this register are system architecture specific. * The maximum latency and minimum grant registers are used to indicate the LAN83C175's desired settings for Latency Timer values. Both registers specify a period of time in units of 1/4 microsecond. For example, if the LAN83C175 ...
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Modem and External Flash RAM Interface and Control Access to the external modem is made through accesses by the host to the EPIC/C. The CardBus configuration space for the modem function must be setup during card initialization. Once this is ...
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Modem Registers Bits Description 80 - NVCTL_m Register 14 - FETPWRMDM: This signal controls the fet power output to the modem. It will power up low, preventing any power from reaching the modem if the output pin is used. 13 ...
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STATUS_m Register 3 and 2 - STS_EVNT: When bit 3 of this register indicates that RDYM has transitioned from When bit 2 of this register indicates that RINGIN has ...
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STSCHG: When this signal is true, it indicates that RDYM or RINGIN transitioned from reset by writing this register location WP: Write protect is not used, and 0 ...
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Physical Connection The number of address bits attached to the modem or external memory is defined by the user. Note: nRESETM is active low at power up, and can be set by a write to a register within the EPIC/C. ...
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OPERATIONAL DESCRIPTION Maximum Guaranteed Ratings Operating Temperature Range......................................................................................... +70 C Storage Temperature Range....................................................................................... - +150 C Lead Temperature Range (soldering, 10 Seconds).................................................................... +325 C Positive Voltage on any pin with respect to Ground .............................................................. V ...
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PARAMETER SYMBOL Input Current Leakage - dc_lk1 Low Input Leakage High Input Leakage Output Current Leakage - dc_lk2 Low Output Leakage High Output Leakage CB Clock - I CBCLK Low Input Voltage High Input Voltage ...
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All Timings are estimated at this time t3 CBCLK nCFRAME t3 t3 nCBE FIGURE 6 - CardBus COMMAND TIMING MASTER NAME MIN MAX t1 t2 2ns 11ns t3 2ns 11ns TIMING DIAGRAMS TARGET MIN MAX DESCRIPTION ...
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CBCLK nCFRAME nCTRDY nCDEVSEL FIGURE 7 - CardBus/nCDEVSEL TIMING MASTER NAME MIN MAX t1 0ns t2 7ns t2 t1 TARGET MIN MAX DESCRIPTION 2ns 11ns (Master) Input hold time from clock (Target) Clock to signal valid delay Input setup to ...
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CBCLK nCIRDY nCTRDY FIGURE 8 - CardBus/nCIRDY AND nCTRDY TIMING MASTER NAME MIN MAX t1 t2 2ns 11ns t3 7ns t4 0ns t5 2ns 11ns TARGET MIN MAX DESCRIPTION 7ns Input setup time to ...
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CBCLK nCFRAME nCTRDY CAD (Add/Data) FIGURE 9 - CardBus/DATA READ TIMING MASTER NAME MIN MAX t1 0ns t2 7ns TARGET MIN MAX DESCRIPTION 2ns 11ns (Master) Input hold time from clock (Target) Clock to signal valid Input ...
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CBCLK nCFRAME nCTRDY CAD (Add/Data) FIGURE 10 - CardBus/DATA WRITE TIMING MASTER NAME MIN MAX t1 t2 2ns 11ns t2 t1 TARGET MIN MAX DESCRIPTION 7ns Input setup time to clock 0ns (Master) Clock to signal valid delay (Target) Input ...
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CBCLK nCFRAME CAD Config Addr nCBE Config Write nCIRDY nCTRDY nCSTOP nCDEVSEL CPAR FIGURE 11 - CardBus - TYPICAL CONFIGURATION WRITE/EPIC/C IS TARGET Config Data BE Addr Par CardBus Bus Cycle Illustration 76 Data Par TRG_CFWR.TD ...
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CBCLK nCFRAME CAD Config Addr nCBE Config Read nCIRDY nCTRDY nCSTOP nCDEVSEL CPAR FIGURE 12 - CardBus - TYPICAL CONFIGURATION READ/EPIC/C IS TARGET Config Data BE Addr Par CardBus Bus Cycle Illustration 77 Data Par TRG_CFRD.TD ...
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CBCLK nCFRAME CAD Address nCBE I/O Read nCIRDY nCTRDY nCSTOP nCDEVSEL CPAR FIGURE 13 - CardBus - TYPICAL I/O READ/EPIC/C IS TARGET BE Addr Par CardBus Bus Cycle Illustration 78 Data Data Par TRG_IORD.TD ...
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CBCLK nCFRAME CAD Address nCBE I/O Write nCIRDY nCTRDY nCSTOP nCDEVSEL CPAR FIGURE 14 - CardBus - TYPICAL I/O WRITE/EPIC/C IS TARGET Data BE Addr Par CardBus Bus Cycle Illustration 79 Data Par TRG_IOWR.TD ...
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CBCLK nCREQ nCGNT nCFRAME CAD Address nCBE Read Cmd nCIRDY nCTRDY nCSTOP nCDEVSEL CPAR FIGURE 15 - CardBus - TYPICAL READ TRANSACTION/SYSTEM MEMORY TO CHIP CardBus Bus Cycle Illustration Data 1 Data Addr Par Data ...
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CBCLK nCREQ nCGNT nCFRAME CAD Address nCBE Write Cmd nCIRDY nCTRDY nCSTOP nCDEVSEL CPAR FIGURE 16 - CardBus - TYPICAL WRITE TRANSACTION/CHIP TO SYSTEM MEMORY Data 1 Data Addr Par Data Par 1 Data Par ...
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TX_CLK TXD TX_EN CRS (1/2 Dup) FIGURE 17 - MII - TRANSMIT TIMING FOR 10/100Mb/s Note: Clock Frequency Changes to 2.5 MHz for 10 Mb/s Nibble Transfers NAME MIN t1, t2 0ns t3 0ns(100Mb/s) 0ns(10Mb/s) t4 0ns(100Mb/s) 0ns(10Mb/ ...
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RX_CLK RXD RX_DV CRS (1/2 Dup) FIGURE 18 - MII - RECEIVE TIMING FOR 100Mb/s Note: Clock Frequency Changes to 2.5MHz for 10Mb/s Nibble Transfers NAME MIN t1, t3 10ns t2, t4, t5 10ns MAX DESCRIPTION Input ...
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RX_CLK RXD t4 RX_DV RX_ER RX_ER expected least 1 clk if CRS (1/2 Dup) error, otherwirse 2 clks FIGURE 19 - MII - RECEIVE ERROR (RX_ER) TIMING FOR 100Mb/s Note: Clock Frequency Changes to 2.5 MHz for ...
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W MDC t1 t2 MDIO Write Data WRITE FIGURE 20 - MII - SERIAL MANAGEMENT WRITE/READ NAME MIN t1 10ns t2 10ns t3 0ns R t3 Read Data READ MAX DESCRIPTION Data ready before the rising edge of MCLK (Setup ...
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HD(7:0) HA(x: FIGURE 21 – MODEM/FLASH RAM WRITE ACCESS Valid Data Valid Address See Table 5 on Page 88 86 ...
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HD(7:0) HA(x: FIGURE 22 - MODEM/FLASH RAM READ ACCESS Valid Data Valid Address See Table 5 on Page ...
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Table 5 - Modem Access Timings NAME MIN (NS) MAX (NS 15- 50- Selectable 2 DESCRIPTION Chip select pulse width. ...
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FIGURE 23 - 208 PIN TQFP, 28X28X1.4 BODY FOOTPRINT See Table 6 on Page 90 89 ...
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Table 6 - Package Dimensions MIN NOMINAL ~ A 0.05 A1 1.35 A2 29.80 30.00 D D/2 14.90 15.00 27.90 28.00 D1 29.80 30.00 E 14.90 15.00 E/2 27.90 28. 0.45 0.60 ~ 1.00 L1 0.50 ...
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91 ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. LAN83C175 Rev. 07/07/97 ...