lan8187 Standard Microsystems Corp., lan8187 Datasheet
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lan8187 Summary of contents
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... IEEE 802.3-2005 compliant register functions Integrated DSP with Adaptive Equalizer Baseline Wander (BLW) Correction LAN8187-JT for 64-pin, TQFP Lead-Free RoHS Compliant Package LAN8187i-JT for (Industrial Temp) 64-pin, TQFP Lead-Free RoHS Compliant Package SMSC LAN8187/LAN8187i LAN8187/LAN8187i ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & ...
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... TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR 2 DATASHEET TM Technology Datasheet SMSC LAN8187/LAN8187i ...
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... Receive Data Across the MII/RMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.4 Jabber Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6 MAC Interface 4.6.1 MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6.2 RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6.3 MII vs. RMII Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7 Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.7.1 Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7.2 Re-starting Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7.3 Disabling Auto-negotiation 4.7.4 Half vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.8 HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.9 Internal +1.8V Regulator Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9.1 Disable the Internal +1.8V Regulator 4.9.2 Enable the Internal +1.8V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.10 (TX_ER/TXD4)/nINT Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SMSC LAN8187/LAN8187i TM Technology 3 DATASHEET Revision 1.5 (01-10-08) ...
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... Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.1.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1.4 DC Characteristics - Input and Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Chapter 8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.1 Magnetics Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.3 Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.4 Evaluation board Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR 4 DATASHEET TM Technology Datasheet SMSC LAN8187/LAN8187i ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Datasheet List of Figures Figure 1.1 LAN8187/LAN8187i System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 1.2 LAN8187/LAN8187i Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2.1 Package Pinout (Top View Figure 4.1 100Base-TX Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4.2 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4.3 Relationship Between Received Data and specific MII Signals . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4.4 Direct cable connection vs. Cross-over cable connection Figure 4.5 PHY Address Strapping on LED’ ...
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... List of Tables Table 2.1 LAN8187/LAN8187i 64-PIN TQFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3.1 MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3.2 LED Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.3 Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.4 Boot Strap Configuration Inputs Table 3.5 General Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.6 10/100 Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.7 Analog References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3.8 No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3.9 Power Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4.1 4B/5B Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4.2 MII/RMII Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 4 ...
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... Table 7.5 MII Bus Interface Signals Table 7.6 LAN Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 7.7 LED Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 7.8 Configuration Inputs Table 7.9 General Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 7.10 Analog References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 7.11 Internal Pull-Up / Pull-Down Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 7.12 100Base-TX Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 7.13 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 9.1 64 Pin TQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SMSC LAN8187/LAN8187i TM Technology 7 DATASHEET Revision 1.5 (01-10-08) ...
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... RMII requires only 6 pins for each MAC to PHY interface plus one common reference clock. The MII requires 16 pins for each MAC to PHY interface. The SMSC LAN8187/LAN8187i is capable of running in RMII mode. Please contact your SMSC sales representative for the latest RMII specification. ...
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... TXD[0..3] TX_EN 100M Rx TX_ER Logic TX_CLK RXD[0..3] RX_DV Receive Section RX_ER RX_CLK 10M Rx CRS Logic COL/CRS_DV MDC MDIO Figure 1.2 LAN8187/LAN8187i Architectural Overview SMSC LAN8187/LAN8187i TM Technology 10M Tx 10M Logic Transmitter Transmit Section 100M Tx 100M Logic Transmitter DSP System: Analog-to- Clock Digital Data Recovery ...
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... Figure 2.1 Package Pinout (Top View) 10 DATASHEET TM Technology Datasheet 48 CRS COL/CRS_DV 48 CRS nINT/TX_ER/TXD4 COL/CRS_DV TXD3 nINT/TX_ER/TXD4 TXD2 TXD3 VDDIO TXD2 TXD1 VDDIO TXD0 TXD1 VSS5 TXD0 TX_EN VSS5 TX_CLK TX_EN AMDIX_EN TX_CLK CH_SELECT AMDIX_EN RX_ER/RXD4 CH_SELECT RX_CLK RX_ER/RXD4 33 RX_DV RX_CLK 33 RX_DV SMSC LAN8187/LAN8187i ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Datasheet Table 2.1 LAN8187/LAN8187i 64-PIN TQFP Pinout PIN NO. PIN NAME 1 GPO0/RMII 2 GPO1/PHYAD4 3 GPO2 4 MODE0 5 MODE1 6 MODE2 7 VSS1 VSS7 10 VSS8 VDD33 14 VDD_CORE 15 VSS2 16 SPEED100/PHYAD0 17 LINK/PHYAD1 ACTIVITY/PHYAD2 20 FDUPLEX/PHYAD3 21 NC ...
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... I Transmit Enable: Indicates that valid data is presented on the TXD[3:0] signals, for transmission. In RMII Mode, only TXD[1:0] have valid data. O Transmit Clock: 25MHz in 100Base-TX mode. 2.5MHz in 10Base-T mode. Note: This signal is not used in RMII Mode 12 DATASHEET TM Technology Datasheet SMSC LAN8187/LAN8187i ...
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... SIGNAL NAME RXD0 RXD1 RXD2 RXD3/ nINTSEL RX_ER/ RXD4 RX_CLK COL/CRS_DV SMSC LAN8187/LAN8187i TM Technology Table 3.1 MII Signals (continued) TYPE DESCRIPTION O Receive Data 0: Bit 0 of the 4 data bits that are sent by the PHY in the receive path. O Receive Data 1: Bit 1 of the 4 data bits that are sent by the PHY in the receive path ...
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... This signal is mux’d with ACTIVITY I/O PHY Address Bit 1: set the default address of the PHY. Note: This signal is mux’d with LINK I/O PHY Address Bit 0: set the default address of the PHY. Note: This signal is mux’d with SPEED100 14 DATASHEET TM Technology Datasheet a SMSC LAN8187/LAN8187i ...
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... MODE2 MODE1 MODE0 REG_EN AMDIX_EN CH_SELECT GPO0/RMII a.On nRST transition high, the PHY latches the state of the configuration pins in this table. SMSC LAN8187/LAN8187i TM Technology TYPE DESCRIPTION I PHY Operating Mode Bit 2: set the default MODE of the PHY. See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page the MODE options ...
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... Strapping Configuration Resistors,” on page 33 Note: See Section 4.6.3, "MII vs. RMII Configuration," on page 26 for more details. Table 3.6 10/100 Line Interface TYPE DESCRIPTION AO Transmit Data: 100Base-TX or 10Base-T differential transmit outputs to magnetics. AO Transmit Data: 100Base-TX or 10Base-T differential transmit outputs to magnetics. 16 DATASHEET TM Technology Datasheet Section 5.4.9.2. Table 4.4, SMSC LAN8187/LAN8187i ...
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... SIGNAL NAME EXRES1 SIGNAL NAME NC SIGNAL NAME AVDD[1-3] AVSS[1-4] VDD_CORE VDD33 VDDIO VSS[1-8] SMSC LAN8187/LAN8187i TM Technology Table 3.6 10/100 Line Interface AI Receive Data: 100Base-TX or 10Base-T differential receive inputs from magnetics. AI Receive Data: 100Base-TX or 10Base-T differential receive inputs from magnetics. Table 3.7 Analog References ...
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... rive Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. 18 DATASHEET TM Technology Datasheet S cra its tic s Table 4.1. Each 4-bit data-nibble SMSC LAN8187/LAN8187i ...
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... R Second nibble of ESD, causes deassertion of CRS if following /T/, else assertion of RX_ER 00100 H Transmit Error Symbol 00110 V INVALID, RX_ER if during RX_DV 11001 V INVALID, RX_ER if during RX_DV SMSC LAN8187/LAN8187i TM Technology Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 0100 0101 0110 ...
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... The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 20 DATASHEET TM Technology Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID SMSC LAN8187/LAN8187i ...
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... This clock is used to extract the serial data from the received signal. 4.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. SMSC LAN8187/LAN8187i TM Technology 100M PLL ...
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... Figure 4.3 Relationship Between Received Data and specific MII Signals Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR data data data data data data data data 22 DATASHEET TM Technology Datasheet T R Idle SMSC LAN8187/LAN8187i ...
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... Detect," on page For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the LAN8187/LAN8187i. TXD[1:0] shall be “00” to indicate idle when TX_EN is deasserted. Values of TXD[1:0] other than “00” when TX_EN is deasserted are reserved for out-of-band signalling (to be defined). Values other than “ ...
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... For RMII, the 2bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid on the rising edge of the RMII REF_CLK. Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR 24 DATASHEET TM Technology Datasheet SMSC LAN8187/LAN8187i ...
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... The PHY drives RX_ER high when a receive error is detected. 4.6.2 RMII The SMSC LAN8187/LAN8187i supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devices incorporating many MACs or PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase ...
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... MII vs. RMII Configuration The LAN8187/LAN8187i must be configured to support the MII or RMII bus for connectivity to the MAC. This configuration is done through the GPO0/RMII pin. MII or RMII mode selection is latched on the rising edge of the internal reset (nreset) based on the strapping of the GPO0/RMII pin. To select MII mode, float the GPO0/RMII pin. To select RMII mode, pull-high with an external resistor (see to VDD33 ...
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... Serial Management Interface (SMI). The results of the negotiation process are reflected in the Speed Indication bits in register 31, as well as the Link Partner Ability Register (Register 5). The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller. SMSC LAN8187/LAN8187i TM Technology Table 4.2, "MII/RMII Signal Table 4.2 MII/RMII Signal Mapping ...
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... Register 0, bit 9 must be set before the new abilities will be advertised. Auto-negotiation can also be disabled via software by clearing register 0, bit 12. Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR 28 DATASHEET TM Technology Datasheet SMSC LAN8187/LAN8187i ...
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... Parallel Detection If the LAN8187/LAN8187i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be Half Duplex per the IEEE standard. ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Table 4.3 Auto-MDIX Control EXTERNAL PINS CH_SELECT DATASHEET TM Technology Datasheet STATUS TX AND RX OUTPUT PINS Auto-MDIX Normal MDI Crossed MDIX Auto-MDIX Normal MDI Crossed MDIX SMSC LAN8187/LAN8187i ...
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... Both a 4.7uF low-ESR and a 0.1uF capacitor must be added at the VDD_CORE pin and placed close to the PHY. This capacitance ensures stability of the internal regulator. SMSC LAN8187/LAN8187i TM Technology 33) is attached from REG_EN to VSS. When both VDDIO and VDDA Section 4 ...
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... Figure 4.5 PHY Address Strapping on LED’s 4.12 Variable Voltage I/O The Digital I/O pins on the LAN8187/LAN8187i are variable voltage to take advantage of low power savings from shrinking technologies. These pins can operate from a low I/O voltage of +1. +3.6V. Due to this low voltage feature addition, the system designer needs to take consideration as for two aspects of their design ...
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... Interrupt 4.13.1 Serial Management Interface (SMI) The Serial Management Interface is used to control the LAN8187/LAN8187i and obtain its status. This interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-specific” registers allowed by the specification. Non-supported registers (7 to 15) will be read as hexadecimal “ ...
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... PHY Address Register Address Data To Phy Write Cycle PHY Address Register Address Data To Phy 34 DATASHEET TM Technology Datasheet ... ... D1 D15 D14 D0 Turn Data Around Data From Phy ... ... D15 D14 D1 D0 Turn Data Around SMSC LAN8187/LAN8187i ...
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Chapter 5 Registers Reset Loopback Speed Select A/N Enable 100Base- 100Base-TX 100Base-TX 10Base-T T4 Full Duplex Half Duplex Full Duplex PHY ID Number (Bits 3-18 of the Organizationally ...
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Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended Next Acknowledge Remote Reserved Page Fault Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended Reserved Table 5.8 ...
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Table 5.11 Register 10 (Extended ...
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Reserved RSVD EDPWRDOWN RSVD LOWSQEN RSVD = Reserved Reserved MIIMODE Table 5.17 Silicon Revision Register 16: Vendor-Specific ...
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Table 5.24 Special Control/Status Indications Register 27: Vendor-Specific AMDIXCTRL Reserved CH_SELECT Table 5.25 Special Internal Testability Control Register 28: Vendor-Specific Table 5.26 ...
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Table 5.28 PHY Special Control/Status Register 31: Vendor-Specific Reserved Autodone Reserved GPO2 GPO1 GPO0 Enable 4B5B Reserved Speed Indication Reserved Scramble Disable 0 ...
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... The mode key is as follows Read/write Self clearing Write only Read only Latch high, clear on read of register Latch low, clear on read of register, NASR = Not Affected by Software Reset X = Either SMSC LAN8187/LAN8187i TM Technology Table 5.29 SMI Register Mapping DESCRIPTION 41 DATASHEET Group Basic ...
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... Table 5.31 Register 1 - Basic Status DESCRIPTION 42 DATASHEET TM Technology Datasheet MODE DEFAULT RW Set by MODE[2:0] bus RW Set by MODE[2:0] bus Set by MODE[2:0] bus RW Set by MODE[2:0] bus MODE DEFAULT SMSC LAN8187/LAN8187i ...
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... Table 5.34 Register 4 - Auto Negotiation Advertisement ADDRESS NAME 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved 4.11:10 Pause Operation SMSC LAN8187/LAN8187i TM Technology DESCRIPTION Table 5.32 Register 2 - PHY Identifier 1 DESCRIPTION Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. OUI=00800Fh Table 5.33 Register 3 - PHY Identifier 2 DESCRIPTION th th ...
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... IEEE 802.3 44 DATASHEET TM Technology Datasheet MODE DEFAULT Set by MODE[2:0] bus Set by MODE[2:0] bus RW Set by MODE[2:0] bus RW 00001 MODE DEFAULT 00001 SMSC LAN8187/LAN8187i ...
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... Reserved 17.11 LOWSQEN 17.10 MDPREBP 17.9 FARLOOPBACK 17.8:7 Reserved SMSC LAN8187/LAN8187i TM Technology DESCRIPTION 1 = fault detected by parallel detection logic fault detected by parallel detection logic 1 = link partner has next page ability 0 = link partner does not have next page ability 1 = local device has next page ability 0 = local device does not have next page ability ...
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... It does not increment in 10Base-T mode. 46 DATASHEET TM Technology Datasheet MODE DEFAULT MODE DEFAULT RW, NASR RW, 000000 NASR RW, XXX for more NASR EVB8700 default 111 RW, PHYAD NASR EVB8700 default 11111 MODE DEFAULT RO 0 SMSC LAN8187/LAN8187i ...
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... Table 5.43 Register 29 - Interrupt Source Flags ADDRESS NAME 29.15:8 Reserved 29.7 INT7 29.6 INT6 29.5 INT5 SMSC LAN8187/LAN8187i TM Technology DESCRIPTION Enables the external AMDIX and CH_SELECT pins 0 - External pins AMDIX_EN and CH_SELECT control the AMDIX Internal bits 27.14 and 27.13 control the AMDIX. Note: Please see Table 4.3, “Auto-MDIX Control,” ...
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... Half-duplex [101]=10Mbps Full-duplex [010]=100Base-TX Half-duplex [110]=100Base-TX Full-duplex 48 DATASHEET TM Technology Datasheet MODE DEFAULT MODE DEFAULT MODE DEFAULT 000 SMSC LAN8187/LAN8187i ...
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... It generates an active low asynchronous interrupt signal on the nINT output whenever certain events are detected as setup by the Interrupt Mask Register 30. The Interrupt system on the SMSC LAN8187/8187i has two modes, a Primary Interrupt mode and an Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set, the difference is how they de-assert the output interrupt signal nINT ...
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... Event to Assert nINT 17.1 ENERGYON Rising 17.1 1.5 Auto-Negotiate Rising 1.5 Complete 1.4 Remote Fault Rising 1.4 1.2 Link Status Falling 1.2 5.14 Acknowledge Rising 5.14 6.4 Parallel Detection Rising 6.4 Fault 6.1 Page Received Rising 6.1 50 DATASHEET TM Technology Datasheet Table 5.47). Condition to Bit to Clear De-Assert. nINT 17.1 low 29.7 1.5 low 29.6 1.4 low 29.5 1.2 high 29.4 5.14 low 29.3 6.4 low 29.2 6.1 low 29.1 SMSC LAN8187/LAN8187i ...
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... Link Integrity Test The LAN8187/LAN8187i performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the reportable link status bit in Serial Management Register 1, and is driven to the LINK LED. ...
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... For the first 16us after coming out of reset, the MII will run at 2.5 MHz. After that it will switch to 25 MHz if auto-negotiation is enabled. Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR The first and possibly the second packet 52 DATASHEET TM Technology Datasheet SMSC LAN8187/LAN8187i ...
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... The four LED signals can be either active-high or active-low. Polarity depends upon the Phy address latched in on reset. The LAN8187/LAN8187i senses each Phy address bit and changes the polarity of the LED signal accordingly. If the address bit is set as level “1”, the LED polarity will be set to an active- low. If the address bit is set as level “ ...
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... All capable. Auto-negotiation enabled. Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Table 5.48 MODE[2:0] Bus DEFAULT REGISTER BIT VALUES REGISTER 0 [13,12,10,8] 0000 0001 1000 1001 1100 1100 N/A X10X 54 DATASHEET TM Technology Datasheet REGISTER 4 [8,7,6,5] N/A N/A N/A N/A 0100 0100 N/A 1111 SMSC LAN8187/LAN8187i ...
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... PHY) MDIO (Write to PHY) PARAMETER DESCRIPTION T1.1 MDC minimum cycle time T1.2 MDC to MDIO (Write) delay T1.3 MDIO (Read) to MDC setup T1.4 MDIO (Read) to MDC hold SMSC LAN8187/LAN8187i TM Technology T1.1 T1.2 Valid Data T1.3 T1.4 Valid Data Figure 6.1 SMI Timing Diagram Table 6.1 SMI Timing Values MIN TYP ...
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... Receive signals setup to RX_CLK rising T2.2 Receive signals hold from RX_CLK rising RX_CLK frequency RX_CLK Duty-Cycle Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Valid Data T2.1 T2.2 MIN TYP MAX DATASHEET TM Technology Datasheet UNITS NOTES ns ns MHz % SMSC LAN8187/LAN8187i ...
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... Transmit signals setup to TX_CLK rising T3.2 Transmit signals hold after TX_CLK rising TX_CLK frequency TX_CLK Duty-Cycle 6.2.2 MII 10Base-T TX/RX Timings 6.2.2.1 10M MII Receive Timing RX_CLK RXD[3:0] RX_DV RX_ER Figure 6.4 10M MII Receive Timing Diagram SMSC LAN8187/LAN8187i TM Technology Valid Data T3.1 T3.2 MIN TYP MAX Valid Data T4.1 T4.2 ...
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... TX_CLK frequency TX_CLK Duty-Cycle Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR MIN TYP MAX Valid Data T5.1 T5.2 MIN TYP MAX DATASHEET TM Technology Datasheet UNITS NOTES ns ns MHz % ns UNITS NOTES ns ns MHz % SMSC LAN8187/LAN8187i ...
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... CRS_DV Figure 6.6 100M RMII Receive Timing Diagram Table 6.6 100M RMII Receive Timing Values PARAMETER DESCRIPTION T6.1 Rising edge of REF_CLK to receive signals output valid T6.2 Rising edge of REF_CLK to receive signals output not valid REF_CLK frequency SMSC LAN8187/LAN8187i TM Technology Valid Data T6.1 T6.2 MIN TYP MAX UNITS 4 2 ...
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... RMII Receive Timing REF_CLK RXD[1:0] CRS_DV Figure 6.8 10M RMII Receive Timing Diagram Revision 1.5 (01-10-08) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Valid Data T8.1 T8.2 MIN TYP MAX Valid Data T9.1 T9.2 60 DATASHEET TM Technology Datasheet UNITS NOTES ns ns MHz SMSC LAN8187/LAN8187i ...
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... T10.1 Transmit signals setup to REF_CLK rising T10.2 Transmit signals hold after REF_CLK rising 6.4 REF_CLK Timing PARAMETER DESCRIPTION REF_CLK frequency REF_CLK Frequency Drift REF_CLK Duty Cycle REF_CLK Jitter SMSC LAN8187/LAN8187i TM Technology MIN TYP MAX Valid Data T10.1 T10.2 MIN TYP MAX ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR T6.1 T6.2 T6.3 T6.4 Figure 6.10 Reset Timing Diagram Table 6.11 Reset Timing Values MIN TYP MAX 100 200 400 20 800 62 DATASHEET TM Technology Datasheet UNITS NOTES clock cycles for 25 MHz clock or 40 clock cycles for 50MHz clock SMSC LAN8187/LAN8187i ...
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... HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing. The device must work normally after the stress has ended, meaning no latch-up on any pins. All pins on the LAN8187 provide +/- 8kV HBM protection. SMSC LAN8187/LAN8187i ...
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... The uncharged electrode first contacts the pin to prepare this test, and then the probe tip is energized. This yields more repeatable results, and is the preferred test method. All pins of the LAN8187 can safely dissipate +/- 8kV contact discharges per the EN61000-4-2 specification without the need for additional board level protection ...
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... Note 7.1 This is calculated with full flexPWR features activated: VDDIO = 1.8V and internal regulator disabled. Note 7.2 Current measurements do not include power applied to the magnetics or the optional external LEDs. Current measurements taken with VDDIO = +3.3V, unless otherwise indicated. SMSC LAN8187/LAN8187i TM Technology VDDA3.3 VDD_CORE POWER POWER ...
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... DATASHEET TM Technology Datasheet +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V 3.6V SMSC LAN8187/LAN8187i ...
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... VDDIO – +0.4 V PHYAD2 VDDIO – +0.4 V PHYAD3 VDDIO – +0.4 V PHYAD4 MODE0 VDDIO – +0.4 V MODE1 VDDIO – +0.4 V MODE2 VDDIO – +0.4 V REG_EN VDDIO – +0.4 V MII SMSC LAN8187/LAN8187i TM Technology Table 7.6 LAN Interface Signals “10BASE-T Transceiver Characteristics,” on page Table 7.7 LED Signals ...
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... V +0 Table 7.10 Analog References PULL-UP OR PULL-DOWN Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-down Pull-down Pull-down Pull-down 68 DATASHEET TM Technology Datasheet +0.4 V VDDIO – +0.4 V +0.4 V 3.7 V +0.4 V VDDIO – +0 SMSC LAN8187/LAN8187i ...
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... Offset from 16 nS pulse width at 50% of pulse peak Note 7.6 Measured differentially. Table 7.13 10BASE-T Transceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Min/max voltages guaranteed as measured with 100 Ω resistive load. Note 7.7 SMSC LAN8187/LAN8187i TM Technology PULL-UP OR PULL-DOWN Pull-down Pull-down Pull-down SYMBOL MIN ...
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... For a list of magnetics selected to operate with the SMSC LAN8187, please refer to the Application note “AN 8-13 Suggested Magnetics”. http://www.smsc.com/main/appnotes.html#Ethernet%20Products 8.2 Application Notes Application examples are given in pdf format on the SMSC LAN8187 web site. The link to the web site is shown below. http://www.smsc.com/main/catalog/lan8187.html Please check the web site periodically for the latest updates. 8.3 Reference Designs The LAN8187 Reference designs are available on the SMSC LAN8187 web site link below ...
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... Integrated 3.3V Regulator APPLICATIONS The EVB8187 Evaluation board simplifies the process of testing and evaluating an Ethernet Connection in your application. The LAN8187 device is installed on the EVB board and all associated circuitry is included, along with all configuration options. The Benefits of adding an external MII interface are: ...
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... REMARKS 1.60 Overall Package Height 0.15 1.45 Body Thickness 12.20 10.20 X body Size 12.20 10.20 Y body Size 0.20 Lead Frame Thickness 0.75 Lead Foot Length ~ Lead Length Lead Pitch o 7 Lead Foot Angle 0.27 Lead Width ~ Lead Shoulder Radius 0.20 Lead Foot Radius 0.08 Coplanarity 72 DATASHEET TM Technology Datasheet Standoff X Span Y Span SMSC LAN8187/LAN8187i ...