lan9500 Standard Microsystems Corp., lan9500 Datasheet
lan9500
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lan9500 Summary of contents
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... Fully compliant with IEEE802.3/802.3u — Integrated Ethernet MAC and PHY — 10BASE-T and 100BASE-TX support — Full- and half-duplex support — Full- and half-duplex flow control SMSC LAN9500/LAN9500i LAN9500/LAN9500i Hi-Speed USB 2.0 to 10/100 Ethernet Controller — Preamble generation and removal — ...
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... Hi-Speed USB 2.0 to 10/100 Ethernet Controller Datasheet LAN9500-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO +70°C TEMP RANGE) LAN9500i-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (-40 TO +85°C TEMP RANGE) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. ...
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... Operational Power Consumption 3.3.5 Customer Evaluation Board Operational Power Consumption . . . . . . . . . . . . . . . . . . . . 23 3.4 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.2 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.3 Reset and Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5.4 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.5.5 Turbo MII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Chapter 4 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SMSC LAN9500/LAN9500i 3 DATASHEET Revision 1.4 (07-07-08) ...
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... List of Figures Figure 1.1 LAN9500/LAN9500i System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW Figure 3.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 3.2 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 3.3 nRESET Reset Pin Timing Figure 3.4 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 3.1 Turbo MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 3.2 Turbo MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 4 ...
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... Table 3.8 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 3.9 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3.10 nRESET Reset Pin Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 3.11 EEPROM Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 3.12 Turbo MII Output Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 3.13 Turbo MII Interface Timing Values Table 3.14 LAN9500/LAN9500i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 4.1 LAN9500/LAN9500i 56-QFN Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SMSC LAN9500/LAN9500i 5 DATASHEET Revision 1.4 (07-07-08) ...
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... Figure 1.1 LAN9500/LAN9500i System Diagram 1.1.1 Overview The LAN9500/LAN9500i is a high performance Hi-Speed USB 2.0 to 10/100 Ethernet controller. With applications ranging from embedded systems, set-top boxes, and PVR’s, to USB port replicators, USB to Ethernet dongles, and test instrumentation, the LAN9500/LAN9500i is a high performance and cost competitive USB to Ethernet connectivity solution ...
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... Hi-Speed USB 2.0 to 10/100 Ethernet Controller Datasheet 1.1.2 USB The USB portion of the LAN9500/LAN9500i integrates a Hi-Speed USB 2.0 device controller and USB PHY. The USB device controller contains a USB low-level protocol interpreter which implements the USB bus protocol, packet generation/extraction, PID/Device ID parsing, and CRC coding/decoding, with autonomous error handling ...
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... EEPROM Controller The LAN9500/LAN9500i contains an EEPROM controller for connection to an external EEPROM. This allows for the automatic loading of static configuration data upon power-on reset, pin reset, or software reset. The EEPROM can be configured to load USB descriptors, USB device configuration, and MAC address. ...
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... TXD2/GPIO6/PORT_SWAP 54 TXD1/GPIO5/RMT_WKP 55 TXD0/GPIO4/EEP_DISABLE 56 NOTE: When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa NOTE: Exposed pad (VSS) on bottom of package must be connected to ground Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW) SMSC LAN9500/LAN9500i SMSC LAN9500/LAN9500i 56 PIN QFN (TOP VIEW) VSS 9 DATASHEET ...
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... Carrier Sense: In internal PHY mode, this pin can be configured to display the respective (PU) internal MII signal. CRS IS Carrier Sense: In external PHY mode, the signal on this pin is input from the external PHY and (PD) indicates a network carrier. GPIO3 IS/O8/ General Purpose I/O 3 OD8 (PU) 10 DATASHEET Datasheet DESCRIPTION SMSC LAN9500/LAN9500i ...
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... PHY Mode) Management Clock 1 (External PHY Mode) General Purpose I/O 2 (Internal PHY Mode Only) SMSC LAN9500/LAN9500i Table 2.1 MII Interface Pins (continued) BUFFER TYPE COL IS/O8 MII Collision Detect: In internal PHY mode, this pin can be configured to display the respective (PU) internal MII signal. COL ...
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... USBDP and USBDM. (PD USBDP maps to the USB D+ line and USBDM maps to the USB D- line USBDP maps to the USB D- line. USBDM maps to the USB D+ line. See Note 2.1 configuration straps. 12 DATASHEET Datasheet DESCRIPTION for more information on for more information on SMSC LAN9500/LAN9500i ...
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... Disable Configuration Strap Transmit Clock (Internal PHY Mode) 1 Transmit Clock (External PHY Mode) SMSC LAN9500/LAN9500i Table 2.1 MII Interface Pins (continued) BUFFER TYPE TXD1 IS/O8 Transmit Data 1: In internal PHY mode, this pin can be configured to display the respective (PD) internal MII signal. TXD1 O8 Transmit Data 1: In external PHY mode, this pin ...
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... EEPROM Clock: This pin drives the EEPROM clock of the external EEPROM. (PD) IS Power Select Configuration Strap: Determines the default power setting when no EEPROM is (PD) present The LAN9500/LAN9500i is bus powered The LAN9500/LAN9500i is self powered. See Note 2.2 configuration straps. Table 2.3 JTAG Pins BUFFER TYPE ...
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... Receive Data 3 (External PHY Mode) NUM PINS NAME SYMBOL PHY Select PHY_SEL 1 SMSC LAN9500/LAN9500i Table 2.3 JTAG Pins (continued) BUFFER TYPE TDO O8 JTAG Data Output: In internal PHY mode, this pin functions as the JTAG data output. O8 PHY Reset (Active-Low): In external PHY mode, this pin functions as the PHY reset output. ...
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... Test 1: This pin must always be connected to VDD33IO for proper operation. TEST2 - Test 2: This pin must always be connected to VSS for proper operation. TEST3 - Test 3: This pin must always be connected to VSS for proper operation. 16 DATASHEET Hi-Speed USB 2.0 to 10/100 Ethernet Controller Datasheet DESCRIPTION SMSC LAN9500/LAN9500i ...
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... HS transmit current level and on-chip termination impedance. Connect to an external 12K 1.0% resistor to ground. P USB PLL +1.8V Supply: This pin must be connected to VDD18CORE for proper operation. Refer to the LAN9500/LAN9500i reference schematic for additional connection information. XI ICLK Crystal Input: External 25 MHz crystal input. Note: ...
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... Refer to the LAN9500/LAN9500i reference schematic for additional connection information. BUFFER TYPE P +3.3V Power Supply for I/O Pins Refer to the LAN9500/LAN9500i reference schematic for connection information. P Digital Core +1.8V Power Supply Output Refer to the LAN9500/LAN9500i reference schematic for connection information. VSS P Common Ground Table 2.8 No-Connect Pins BUFFER TYPE NC - ...
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... RXP 20 7 VDD33A 21 8 EXRES 22 9 VDD33A 23 10 VDD18PLL 24 11 USBDM 25 12 USBDP 26 13 TEST2 SMSC LAN9500/LAN9500i PIN PIN NAME NUM PIN NAME VDD33A 29 EECLK/ PWR_SEL USBRBIAS 30 EECS VDD18USBPLL 31 EEDO/ AUTOMDIX_EN XI 32 EEDI XO 33 TEST3 VBUS_DET 34 PHY_SEL VDD18CORE 35 VDD33IO ...
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... Unless otherwise noted in the pin description, internal pull-downs are always enabled. Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the LAN9500/LAN9500i. When connected to a load that must be pulled low, an external resistor must be added. AI Analog input ...
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... Note, device signals are NOT 5 volt tolerant unless specified otherwise. 3.2 Operating Conditions** Supply Voltage (VDD33A, VDD33BIAS, VDD33IO +3.3V +/- 300mV Ambient Operating Temperature in Still Air (T **Proper operation of LAN9500/LAN9500i is guaranteed only within the ranges specified in this section. SMSC LAN9500/LAN9500i (Note 3. +3.6V (Note (Note ) ...
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... Power Consumption This section details the power consumption of LAN9500/LAN9500i as measured during various modes of operation. Power consumption values are provided for both the device-only, and for the device plus Ethernet components. Power dissipation is determined by temperature, supply voltage, and external source/sink requirements. 3.3.1 SUSPEND0 Table 3 ...
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... Power Dissipation (Device and Ethernet components) 3.3.5 Customer Evaluation Board Operational Power Consumption Table 3.5 Customer Evaluation Board Operational Power Consumption - Supply and Current @3.3V PARAMETER 100BASE-TX Full Duplex (USB High-Speed) Total SMSC Customer Evaluation Board Current Consumption SMSC LAN9500/LAN9500i MIN TYPICAL 137.3 453.0 591.2 99.2 327 ...
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... TBD TBD 0.4 VDD33IO - 0.4 0.4 0.4 VDD33IO - 0.4 0.4 -0.3 0.5 1.4 3.6 24 DATASHEET Datasheet UNITS NOTES Schmitt trigger V Schmitt trigger mV uA Note 3 Schmitt trigger V Schmitt trigger mV uA Note 3.5 uA Note 3.5, Note 3 8mA -8mA 8mA 12mA -12mA 12mA OL Note 3 SMSC LAN9500/LAN9500i ...
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... Offset from 16nS pulse width at 50% of pulse peak. Note 3.10 Measured differentially. Table 3.8 10BASE-T Transceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Note 3.11 Min/max voltages guaranteed as measured with 100Ω resistive load. SMSC LAN9500/LAN9500i SYMBOL MIN TYP MAX V 950 ...
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... AC Specifications This section details the various AC timing specifications of the LAN9500/LAN9500i. Note: The MII timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification for detailed MII timing information. Note: The USBDP and USBDM pin timing adheres to the USB 2.0 specification. Refer to the Universal Serial Bus Revision 2 ...
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... VDD33IO Configuration Straps Figure 3.2 Power-On Configuration Strap Valid Timing Table 3.9 Power-On Configuration Strap Valid Timing SYMBOL t Configuration strap valid time cfg SMSC LAN9500/LAN9500i 2.0V t cfg DESCRIPTION 27 DATASHEET MIN TYP MAX ...
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... Configuration strap pins hold after nRESET deassertion csh t Output drive after deassertion odad Revision 1.4 (07-07-08) t rstia t t css csh t odad Figure 3.3 nRESET Reset Pin Timing DESCRIPTION 28 DATASHEET Hi-Speed USB 2.0 to 10/100 Ethernet Controller Datasheet MIN TYP MAX UNITS 1 uS 200 SMSC LAN9500/LAN9500i ...
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... Hi-Speed USB 2.0 to 10/100 Ethernet Controller Datasheet 3.5.4 EEPROM Timing The following specifies the EEPROM timing requirements for LAN9500/LAN9500i: EECS t cshckh EECLK EEDO EEDI EEDI (VERIFY) SYMBOL DESCRIPTION t EECLK Cycle time ckcyc t EECLK High time ckh t EECLK Low time ckl t EECS high before rising edge of EECLK ...
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... Note 3.12 These values satisfy the MII specification requirement clock to output delay. Note 3.13 Timing was designed for system load between 5 pf and 15 pf. Revision 1.4 (07-07-08) Hi-Speed USB 2.0 to 10/100 Ethernet Controller t txhold Figure 3.1 Turbo MII Output Timing MIN 1.5 30 DATASHEET Datasheet MAX UNITS NOTES 12.5 ns Note 3.12 Note 3.13 ns Note 3.13 SMSC LAN9500/LAN9500i ...
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... RXCLK t RXD and RXDV hold time after the rising edge rxhold of RXCLK Note 3.14 These values satisfy the 10-ns setup and hold time requirements that are necessary for the MII specification. SMSC LAN9500/LAN9500i t t rxhold rxsetup Figure 3.2 Turbo MII Input Timing MIN 5.5 ...
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... Clock Circuit LAN9500/LAN9500i can accept either a 25MHz crystal (preferred 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum. ...
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... Hi-Speed USB 2.0 to 10/100 Ethernet Controller Datasheet Chapter 4 Package Outline Figure 4.1 LAN9500/LAN9500i 56-QFN Package Table 4.1 LAN9500/LAN9500i 56-QFN Dimensions MIN NOMINAL A 0. 0.00 0. D/E 7.85 8.00 D1/E1 7.55 - D2/E2 5.75 5. 0.18 0.25 e 0.50 BSC Notes: 1. All dimensions are in millimeters unless otherwise noted. 2. Position tolerance of each terminal and exposed pad is +/- 0. maximum material condition. Dimension “ ...
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... Figure 4.2 LAN9500/LAN9500i 56-QFN Recommended PCB Land Pattern Revision 1.4 (07-07-08) Hi-Speed USB 2.0 to 10/100 Ethernet Controller 34 DATASHEET Datasheet SMSC LAN9500/LAN9500i ...