tda19978ahv NXP Semiconductors, tda19978ahv Datasheet
tda19978ahv
Available stocks
Related parts for tda19978ahv
tda19978ahv Summary of contents
Page 1
TDA19978A Quad HDMI 1.3a receiver interface with equalizer (HDTV up to 1080p UXGA for PC formats) Rev. 02 — 18 August 2008 1. General description The TDA19978A is a four input HDMI 1.3a compliant receiver with embedded EDID ...
Page 2
... NXP Semiconductors 2. Features I Complies with the HDMI 1.3a, DVI 1.0, CEA-861-D and HDCP 1.2 standards I Four (quad) independent HDMI inputs the HDMI frequency of 235 MHz I Embedded auto-adaptive equalizer on all HDMI links I EDID memory: 253 shared bytes and three bytes dedicated to each HDMI input ...
Page 3
... [ activity on video port output. 5. Ordering information Table 2. Ordering information Type number Package Name TDA19978AHV HLQFP144 TDA19978A_2 Objective data sheet Quad HDMI 1.3a receiver with digital processing I High-End TV I Home theater amplifier I DVD recorder I ...
Page 4
HDMI A (channels 0/1/2) TERMINATION RESISTANCE HDMI A (channel A) CONTROL RRX1 HDMI B (channels 0/1/2) TERMINATION RESISTANCE HDMI B (channel B) CONTROL HDMI C (channels 0/1/2) TERMINATION RESISTANCE HDMI C (channel C) CONTROL RRX2 HDMI D (channels 0/1/2) TERMINATION ...
Page 5
... DDH(1V8) RXD1+ RXD1 V SSH RXC1 RXC1+ V DDH(3V3) RXD2+ RXD2 TDA19978A_2 Objective data sheet Quad HDMI 1.3a receiver with digital processing 1 TDA19978AHV 36 Pin configuration (HLQFP144) Pin description [1] Pin Type Description 1 G ground for the digital core 2 I power-down control input (active HIGH HDMI receiver supply voltage ...
Page 6
... NXP Semiconductors Table 3. Symbol V SSH RXC2 RXC2 DDC(1V8) V DDO(3V3) VCLK V SSO CS/FREF VS/VREF HS/HREF DE VP[0] V SSC VP[1] VP[2] VP[3] V DDO(3V3) V DDC(1V8) V SSO VP[4] VP[5] VP[6] VP[7] VP[8] VP[9] VP[10] VP[11] V DDO(3V3) VP[12] V SSO VP[13] VP[14] VP[15] VP[16] VP[17] VP[18] VP[19] TDA19978A_2 Objective data sheet Quad HDMI 1.3a receiver with digital processing Pin description …continued [1] Pin Type Description 24 G HDMI receiver ground ...
Page 7
... NXP Semiconductors Table 3. Symbol VP[20] V DDO(3V3) V DDC(1V8) V SSO VP[21] VP[22] VP[23] VP[24] VP[25] VP[26] VP[27] V SSC V DDO(3V3) VP[28] VP[29] V SSO ACLK AP0 AP1 AP2/CTL0 AP3/CTL1 AP4/WS/CTL2 V DDO(3V3) AP5/SYSCLK/CTL3 V SSO V DDH(3V3) V DDH(3V3) V SSH V DDH(1V8) V SSH V DDC(1V8) XTALOUT XTALIN/MCLK V DDI(3V3) TDA19978A_2 Objective data sheet Quad HDMI 1.3a receiver with digital processing Pin description … ...
Page 8
... NXP Semiconductors Table 3. Symbol VAI SDA SCL HSDAA HSCLA HSDAB HSCLB TEST0 V DDH(3V3) V SSH RRX1 V DDC(1V8) V DDH(1V8) V SSC A0 V DDH(3V3) RXBC+ RXBC V SSH RXAC RXAC+ V DDH(3V3) RXB0+ RXB0 V SSH RXA0 RXA0+ V DDH(1V8) RXB1+ RXB1 V SSH RXA1 RXA1+ V DDH(3V3) RXB2+ RXB2 V SSH ...
Page 9
... NXP Semiconductors Table 3. Symbol V SSH V DDC(1V8) V DDC(1V8) HSDAC HSCLC HSDAD HSCLD V DDI(3V3) RRX2 V DDH(1V8) Exposed die pad [ power supply ground input output and I/O = input/output. [2] Connected to the ground of the HDMI receiver (V 8. Functional description The TDA19978A converts digital data streams input by the HDMI sources into parallel digital data for use by media and video signal processing integrated circuits such as NXP Semiconductors’ ...
Page 10
... NXP Semiconductors 8.3 Termination resistance control The HDMI receiver input contains a termination resistance control set by an external resistor connected between pins RRXx and V and for inputs C and D. Typically, the characteristic impedance is 50 default value of the external terminal control resistor 8.4 Equalizer The auto-adaptive equalizer automatically measures and selects the settings which provide the best signal quality for each cable ...
Page 11
... NXP Semiconductors 8.9 Upsample The HDMI source can use YCbCr 4:2:2 pixel encoding which enables the number of bits allocated per component to be increased up to 12. The upsample function transforms this 12-bit YCbCr 4:2:2 data stream into a 12-bit YCbCr 4:4:4 data stream by repeating or linearly interpolating the chrominance pixels Cb and Cr. ...
Page 12
... NXP Semiconductors Table 4. Audio port AP5 AP4 AP3 AP2 AP1 AP0 ACLK [1] Can be activated with the I Table 5. Audio port AP5 AP4 AP3 AP2 AP1 AP0 ACLK [1] Can be activated with the I Table 6. Audio port AP5 AP4 AP3 AP2 AP1 AP0 ACLK [1] Can be activated with the I [ SDx and S/PDIFx relates to the actual frame ...
Page 13
... NXP Semiconductors 8.13 Sync timing measurement To assist input format recognition, the vertical/horizontal periods and the horizontal pulse width are measured based on the externally generated MCLK frequency (27 MHz crystal). This function has an accuracy of 1 LSB = 1 8.14 Format measurement timing The TDA19978A includes an improved system for accurate recognition of PC and TV formats ...
Page 14
... NXP Semiconductors 8.19 4:2:2 formatter The 4:2:2 formatter contains the YCbCr 4:2:2 semi-planar and the YCbCr 4:2:2 ITU-R BT.656 formatting functions. The selection of these functions is made using the 2 I C-bus. • In YCbCr 4:2:2 mode: the data frequency for the Y signal is equal to the pixel clock frequency. While the data frequency for the Cb and Cr signals is equal to half the pixel clock frequency • ...
Page 15
... NXP Semiconductors 8.24 Power management The TDA19978A can use one of three Power-down modes: • level 0: full Power-down mode • level 1: internal EDID memory with I • level 2: internal EDID memory with I enabled The user can activate these different modes with pin PD or using I • ...
Page 16
... NXP Semiconductors 8.25.2 EDID memory shared over three HDMI inputs (1) 253 bytes Fig C-bus protocol The TDA19978A is a slave I and protocol for I Bit A0 of the C-bus address is given in Table TDA19978A_2 Objective data sheet Quad HDMI 1.3a receiver with digital processing ...
Page 17
... NXP Semiconductors 10. Limiting values Table 8. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DDx(3V3) V DDx(1V8 stg T amb esd 11. Thermal characteristics Table 9. Symbol R th(j-a) R th(j-c) 12. Characteristics Table 10. Characteristics V = 3.135 V to 3.465 V; V DDH(3V3 1. 1. DDC(1V8) amb ...
Page 18
... NXP Semiconductors Table 10. Characteristics …continued V = 3.135 V to 3.465 V; V DDH(3V3 1. 1. DDC(1V8) amb V and V = 1.8 V and T DDH(1V8) DDC(1V8) Symbol Parameter I input supply current (3.3 V) DDI(3V3) I output supply current (3.3 V) DDO(3V3) I core supply current (1.8 V) DDC(1V8) V supply voltage difference between DD(3V3-3V3) two 3.3 V supplies V supply voltage difference between DD(1V8-1V8) two 1 ...
Page 19
... NXP Semiconductors Table 10. Characteristics …continued V = 3.135 V to 3.465 V; V DDH(3V3 1. 1. DDC(1V8) amb V and V = 1.8 V and T DDH(1V8) DDC(1V8) Symbol Parameter Timing output: pins AP[5:0] with respect to ACLK data output set-up time su(Q) t data output hold time h(Q) LV-TTL digital outputs: pins VP[29:0], VCLK, AP[5:0], ACLK, DE, HS, VS, HREF, VREF, FREF; C ...
Page 20
... NXP Semiconductors Fig 5. Fig 6. TDA19978A_2 Objective data sheet Quad HDMI 1.3a receiver with digital processing VCLK VP[29:0] Output timing diagram pin VCLK on pins VP[29:0] ACLK AP[5:0] Output timing diagram pin ACLK on pins AP[5:0] Rev. 02 — 18 August 2008 TDA19978A su(Q) 2 h(Q) 001aah368 su(Q) 2 h(Q) 001aah369 © NXP B.V. 2008. All rights reserved. ...
Page 21
... NXP Semiconductors 13. Output video port formats (mapping examples) The following tables are examples of output formats that can be used with the video driver’s port swap function. Table 11. Output in 12-bit video port format (mapping example 1) Signal YCbCr 4:2:2 semi-planar VP[29] Y [11 VP[28] Y [10] ...
Page 22
... NXP Semiconductors Table 12. Output in 12-bit video port format (mapping example 2) Signal YCbCr 4:2:2 semi-planar VP[29] Cb[11] Cr[11] VP[28] Cb[10] Cr[10] VP[27] Cb[9] Cr[9] VP[26] Cb[8] Cr[8] VP[25] Cb[7] Cr[7] VP[24] Cb[6] Cr[6] VP[23] Cb[5] Cr[5] VP[22] Cb[4] Cr[4] VP[21] Cb[3] Cr[3] VP[20] Cb[2] Cr[2] VP[19] Cb[1] Cr[1] VP[18] Cb[0] Cr[0] VP[17] Y [11] Y [11 VP[16] Y [10] Y [10 VP[15] Y [ VP[14] Y [ VP[13] Y [ VP[12] Y [ VP[11] Y [ VP[10] Y [ VP[9] Y [ VP[8] Y [2] ...
Page 23
... NXP Semiconductors Table 13. Output in 10-bit video port format (mapping example 1) Signal RGB YCbCr 4:4:4 VP[29] G[11] Y[11] VP[28] G[10] Y[10] VP[27] G[9] Y[9] VP[26] G[8] Y[8] VP[25] G[7] Y[7] VP[24] G[6] Y[6] VP[23] G[5] Y[5] VP[22] G[4] Y[4] VP[21] G[3] Y[3] VP[20] G[2] Y[2] VP[19] R[11] Cr[11] VP[18] R[10] Cr[10] VP[17] R[9] Cr[9] VP[16] R[8] Cr[8] VP[15] R[7] Cr[7] VP[14] R[6] Cr[6] VP[13] R[5] Cr[5] VP[12] R[4] Cr[4] VP[11] R[3] Cr[3] VP[10] R[2] Cr[2] VP[9] B[11] Cb[11] VP[8] B[10] Cb[10] VP[7] B[9] Cb[9] VP[6] B[8] Cb[8] VP[5] B[7] Cb[7] VP[4] B[6] Cb[6] VP[3] B[5] Cb[5] VP[2] B[4] Cb[4] VP[1] B[3] Cb[3] VP[0] B[2] Cb[2] [ high-impedance LOW-level; depending on the driver configuration. TDA19978A_2 Objective data sheet Quad HDMI 1.3a receiver with digital processing [1] YCbCr 4:2:2 semi-planar YCbCr 4:2:2 ITU-R BT.656 Y [11] Y [11] Z [10] Y [10] ...
Page 24
... NXP Semiconductors Table 14. Output in 10-bit video port format (mapping example 2) Signal RGB YCbCr 4:4:4 VP[29] B[11] Cb[11] VP[28] B[10] Cb[10] VP[27] B[9] Cb[9] VP[26] B[8] Cb[8] VP[25] B[7] Cb[7] VP[24] B[6] Cb[6] VP[23] B[5] Cb[5] VP[22] B[4] Cb[4] VP[21] B[3] Cb[3] VP[20] B[2] Cb[2] VP[19] G[11] Y[11] VP[18] G[10] Y[10] VP[17] G[9] Y[9] VP[16] G[8] Y[8] VP[15] G[7] Y[7] VP[14] G[6] Y[6] VP[13] G[5] Y[5] VP[12] G[4] Y[4] VP[11] G[3] Y[3] VP[10] G[2] Y[2] VP[9] R[11] Cr[11] VP[8] R[10] Cr[10] VP[7] R[9] Cr[9] VP[6] R[8] Cr[8] VP[5] R[7] Cr[7] VP[4] R[6] Cr[6] VP[3] R[5] Cr[5] VP[2] R[4] Cr[4] VP[1] R[3] Cr[3] VP[0] R[2] Cr[2] [ high-impedance LOW-level; depending on the driver configuration. TDA19978A_2 Objective data sheet Quad HDMI 1.3a receiver with digital processing [1] YCbCr 4:2:2 semi-planar Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y [11] Y [11 [10] Y [10 [9] Y [9] ...
Page 25
... NXP Semiconductors Table 15. Output in 8-bit video port format (mapping example 1) Signal RGB YCbCr 4:4:4 VP[29] G[11] Y[11] VP[28] G[10] Y[10] VP[27] G[9] Y[9] VP[26] G[8] Y[8] VP[25] G[7] Y[7] VP[24] G[6] Y[6] VP[23] G[5] Y[5] VP[22] G[4] Y[4] VP[21] R[11] Cr[11] VP[20] R[10] Cr[10] VP[19] R[9] Cr[9] VP[18] R[8] Cr[8] VP[17] R[7] Cr[7] VP[16] R[6] Cr[6] VP[15] R[5] Cr[5] VP[14] R[4] Cr[4] VP[13] B[11] Cb[11] VP[12] B[10] Cb[10] VP[11] B[9] Cb[9] VP[10] B[8] Cb[8] VP[9] B[7] Cb[7] VP[8] B[6] Cb[6] VP[7] B[5] Cb[5] VP[6] B[4] Cb[4] VP[5] Z/L Z/L VP[4] Z/L Z/L VP[3] Z/L Z/L VP[2] Z/L Z/L VP[1] Z/L Z/L VP[0] Z/L Z/L [ high-impedance LOW-level; depending on the driver configuration. TDA19978A_2 Objective data sheet [1] [1] YCbCr 4:2:2 semi-planar Y [11] Y [11 [10] Y [10 [ [ [7] ...
Page 26
... NXP Semiconductors Table 16. Output in 8-bit video port format (mapping example 2) [1] Signal RGB YCbCr 4:4:4 VP[29] B[11] Cb[11] VP[28] B[10] Cb[10] VP[27] B[9] Cb[9] VP[26] B[8] Cb[8] VP[25] B[7] Cb[7] VP[24] B[6] Cb[6] VP[23] B[5] Cb[5] VP[22] B[4] Cb[4] VP[21] G[11] Y[11] VP[20] G[10] Y[10] VP[19] G[9] Y[9] VP[18] G[8] Y[8] VP[17] G[7] Y[7] VP[16] G[6] Y[6] VP[15] G[5] Y[5] VP[14] G[4] Y[4] VP[13] R[11] Cr[11] VP[12] R[10] Cr[10] VP[11] R[9] Cr[9] VP[10] R[8] Cr[8] VP[9] R[7] Cr[7] VP[8] R[6] Cr[6] VP[7] R[5] Cr[5] VP[6] R[4] Cr[4] VP[5] Z/L Z/L VP[4] Z/L Z/L VP[3] Z/L Z/L VP[2] Z/L Z/L VP[1] Z/L Z/L VP[0] Z/L Z/L [ high-impedance LOW-level; depending on the driver configuration. TDA19978A_2 Objective data sheet [1] [1] YCbCr 4:2:2 semi-planar Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y [11] Y [11 [10] Y [10 [ [ ...
Page 27
... NXP Semiconductors 14. Example of supported video formats Table 17. Standard [2] 576i [4] 480i 576p 480p 720p 1080i 1080p 0.31M3 VGA 0.48M3 SVGA 0.48M3-R 0.41M9 0.79M3 XGA 0.79M3-R XGA 1.00M3 0.98M9-R TDA19978A_2 Objective data sheet Quad HDMI 1.3a receiver with digital processing Example of supported video formats ...
Page 28
... NXP Semiconductors Table 17. Standard 0.98M9 1.02MA-R 1.02MA 1.23M3 1.31M4 SXGA 1.04M9 1.04M9-R 1.47M3-R 1.47M3 1.29MA-R 1.29MA 1.92M3 UXGA 1.76MA-R 1.76MA 2.30MA-R [1] Pixel clock rate corresponds to VCLK output for 4:4:4 format and 4:2:2 semi-planar; VCLK / 2 for 4:2:2 ITU-R BT.656 format. The pixel clock rate can be determined by: ...
Page 29
... VP[0] 36 Each supply voltage pin should be decoupled with a 100 nF capacitor. Fig 7. Application diagram TDA19978A_2 Objective data sheet Quad HDMI 1.3a receiver with digital processing HDMI inputs A and B TDA19978AHV GNDC control outputs and video port outputs Rev. 02 — 18 August 2008 TDA19978A V DDH(1V8) 108 1.8V ...
Page 30
... NXP Semiconductors 16. Package outline HLQFP144: plastic thermal enhanced low profile quad flat package; 144 leads; body 1.4 mm; exposed die pad y exposed die pad 108 109 E h pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max ...
Page 31
... NXP Semiconductors 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
Page 32
... NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
Page 33
... NXP Semiconductors Fig 9. For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 20. Acronym ACR AVR AWG DAC DDC-bus DSD DST DTS-HD DVD DVI EDID HBM HBR HDCP HDMI HDTV L-PCM LSB LV-TTL ...
Page 34
... NXP Semiconductors Table 20. Acronym OBA OTP PAL PLL RGB SACD SVGA SXGA S/PDIF UXGA VGA WUXGA XGA YCbCr YUV 19. Revision history Table 21. Revision history Document ID Release date TDA19978A_2 20080818 • Modifications: Added • Added • Change to f • Change to row heading LV-TTL digital outputs. ...
Page 35
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 36
... NXP Semiconductors 22. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 4. Audio port configuration (Layout .12 Table 5. Audio port configuration (Layout .12 Table 6. Audio port configuration for HBR and DST packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2 Table 7. I C-bus slave address . . . . . . . . . . . . . . . . . . .16 Table 8 ...
Page 37
... NXP Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 9 8.1 Software Drivers . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2 HDMI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.3 Termination resistance control . . . . . . . . . . . . 10 8.4 Equalizer 8.5 Activity detection 8.6 High-bandwidth digital content protection ...