at89c51re2-slsem ATMEL Corporation, at89c51re2-slsem Datasheet

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at89c51re2-slsem

Manufacturer Part Number
at89c51re2-slsem
Description
At89c51re2 8-bit Flash Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
Features
Note:
80C52 Compatible
ISP (In-System Programming) Using Standard V
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
Boot ROM Contains Serial Loader for In-System Programming
High-speed Architecture
128K bytes On-chip Flash Program/Data Memory
On-chip 8192 bytes Expanded RAM (XRAM)
Dual Data Pointer
Extended stack pointer to 512 bytes
Variable Length MOVX for Slow RAM/Peripherals
Improved X2 Mode with Independant Selection for CPU and Each Peripheral
Keyboard Interrupt Interface on Port 1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
Programmable Counter Array with:
Asynchronous Port Reset
Two Full Duplex Enhanced UART with Dedicated Internal Baud Rate Generator
Low EMI (inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag
Power Control Modes: Idle Mode, Power-down Mode
Power Supply: 2.7V to 5.5V
Temperature Ranges: Industrial (-40 to +85°C)
Packages: PLCC44, VQFP44, VQFP64
– 8051 Instruction Compatible
– Six 8-bit I/O Ports (64 pins or 68 Pins Versions)
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit Timer/Counters
– 256 bytes Scratch Pad RAM
– 11 Interrupt Sources With 4 Priority Levels
– In Standard Mode:
– In X2 Mode (6 Clocks/Machine Cycle)
– 128 bytes Page Write with auto-erase
– 100k Write Cycles
– Software Selectable Size (0, 256, 512, 768, 1024, 1792, 2048, 4096, 8192 bytes)
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
40 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)
20 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)
1. Contact Atmel Sales for availability.
(1)
CC
Power Supply
8-bit Flash
Microcontroller
AT89C51RE2
7663B–8051–03/07
1

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at89c51re2-slsem Summary of contents

Page 1

... Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag • Power Control Modes: Idle Mode, Power-down Mode • Power Supply: 2.7V to 5.5V • Temperature Ranges: Industrial (-40 to +85°C) • Packages: PLCC44, VQFP44, VQFP64 Note: 1. Contact Atmel Sales for availability. Power Supply CC (1) 8-bit Flash Microcontroller AT89C51RE2 7663B–8051–03/07 1 ...

Page 2

... V pin. CC The AT89C51RE2 retains all features of the Atmel 80C52 with 256 bytes of internal RAM, a 10-source 4-level interrupt controller and three timer/counters. In addition, the AT89C51RE2 has a Programmable Counter Array, an XRAM of 8192 bytes, a Hardware Watchdog Timer, SPI and Keyboard, two serial channels that facili- ...

Page 3

Block Diagram Figure 1. Block Diagram (2) (2) XTALA1 XTALA2 EUART XTALB1(1) XTALB2 CPU ALE/ PROG PSEN EA (2) Timer 0 RD Timer 1 (2) WR (2) (2) 7663B–8051–03/07 (1) Flash RAM XRAM PCA 128Kx8 256x8 8192 x 8 C51 ...

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... P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 P6.1/TxD_1 33 ALE 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 AT89C51RE2 VQFP44 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA P6.1/TxD_1 ALE PSEN P2 ...

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... P5.5 1 P0.3/AD3 2 P0.2/AD2 3 P5.6 4 P0.1/AD1 5 P0.0/AD0 6 AT89C51RE2 P5.7 7 VQFP64 VCC 8 Rx_OCD 9 P1.0/T2 10 P4.0 11 P1.1/T2EX/SS# 12 P1.2/ECI 13 P1.3/CEX0 14 P4.1 15 P1.4/CEX1 16 7663B–8051–03/07 48 P2.4/A12 47 P2.3/A11 46 P4.7 45 P2.2/A10 44 P2.1/A9 43 P2.0/A8 42 P4.6 41 Tx_OCD 40 VSS 39 P4.5 38 XTAL1 37 XTAL2 36 P3.7/RD# 35 P4.4 34 P3.6/WR# 33 P4.3 NIC: Not Internaly Connected 5 ...

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... P3.0-P3.7 11, 5, 13-19 7- AT89C51RE2 6 Table 2. Pin Description Type Name and Function I Ground: 0V reference I Optional Ground: Contact the Sales Office for ground connection. I Power Supply: This is the power supply voltage for normal, idle and power-down operation I/O Port 0: Port open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs ...

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Pin Number Mnemonic LCC VQFP 1 P6.0-P6.1 12, Reset 10 4 ALE/PROG 33 27 PSEN XTAL1 21 15 XTAL2 ...

Page 8

... SFR Mapping AT89C51RE2 8 The Special Function Registers (SFRs) of the AT89C51RE2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, P4, P5, P6 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...

Page 9

Table 3. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer DPL 82h Data Pointer Low byte DPH 83h Data Pointer High byte Table 4. System Management ...

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... CDh Timer/Counter 2 High Byte TL2 CCh Timer/Counter 2 Low Byte Table 9. PCA SFRs Mnemo -nic Add Name CCON D8h PCA Timer/Counter Control CMOD D9h PCA Timer/Counter Mode CL E9h PCA Timer/Counter Low byte AT89C51RE2 FPL3 FPL2 FPL1 FPL0 FMR ...

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Table 9. PCA SFRs (Continued) Mnemo -nic Add Name CH F9h PCA Timer/Counter High byte CCAPM0 DAh PCA Timer/Counter Mode 0 CCAPM1 DBh PCA Timer/Counter Mode 1 CCAPM2 DCh PCA Timer/Counter Mode 2 CCAPM3 DDh PCA Timer/Counter Mode 3 CCAPM4 ...

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... SPI Status SPDAT C5h SPI Data Table 12. Keyboard Interface SFRs Mnemonic Add Name KBLS 9Ch Keyboard Level Selector KBE 9Dh Keyboard Input Enable KBF 9Eh Keyboard Flag Register AT89C51RE2 SPR2 SPEN SSDIS MSTR SPIF OVR MODF SPD7 SPD6 SPD5 SPD4 ...

Page 13

Table 13. SFR Mapping Bit addressable 0/8 P6 F8h XXXX XX11 B F0h 0000 0000 P5 E8h 1111 1111 ACC E0h 0000 0000 CCON D8h 00X0 0000 PSW D0h 0000 0000 T2CON C8h 0000 0000 XXXX XX00 SCON_1 U2(AUXR1.5) =0 ...

Page 14

... ALE disabling • Enhanced features on the UART and the timer 2 The AT89C51RE2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...

Page 15

Figure 3. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode 7663B–8051–03/07 F OSC X2 Mode The X2 bit in the CKCON0 register (see Table 14) allows a switch from 12 clock periods per instruction to 6 clock ...

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... AT89C51RE2 16 Table 14. CKCON0 Register CKCON0 - Clock Control Register (8Fh WDX2 PCAX2 Bit Bit Number Mnemonic Description 7 - Reserved Watchdog Clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit 6 WDX2 has no effect). Cleared to select 6 clock periods per peripheral clock cycle. ...

Page 17

Table 15. CKCON1 Register CKCON1 - Clock Control Register (AFh Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved ...

Page 18

... Dual Data Pointer Register DPTR Figure 4. Use of Dual Pointer 7 AUXR1(A2H) AT89C51RE2 18 The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an exter- nal data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1 ...

Page 19

Table 16. AUXR1 register AUXR1- Auxiliary Register 1(0A2h EES SP9 U2 Bit Bit Number Mnemonic Description Enable Extended Stack This bit allows the selection of the stack extended mode. 7 EES Set to enable the extended ...

Page 20

... AT89C51RE2 20 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a par- ticular state, but simply toggles it ...

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... FCB Hardware Security (1 byte) HSB Column Latches (128 bytes) 1FFFFh 00000h 7663B–8051–03/07 AT89C51RE2 features several on-chip memories: • Flash memory : containing 128 Kbytes of program memory (user space) organized into 128 bytes pages. • Boot ROM: 4K bytes for boot loader. ...

Page 22

... AT89C51RE2 devices have expanded RAM in external data space configurable up to 8192bytes (see Table 17.). The AT89C51RE2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable ...

Page 23

XRAM. • With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0 the ...

Page 24

... Registers AT89C51RE2 24 Table 17. AUXR Register AUXR - Auxiliary Register (8Eh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Pulse length ...

Page 25

Extended Stack Logical MCU Address SP Value FFFFh XRAM 0000h FFh FFh 256 bytes IRAM 256 SP values rollover within 256B of IRAM 00h 00h Standard C51 Stack mode EES = 0 7663B–8051–03/07 The lowest bytes of the XRAM may ...

Page 26

... AT89C51RE2 26 Bit Bit Number Mnemonic Description P4 bit addressable 5 U2 Clear to map SCON_1 register at C0h sfr address Set to map P4 port register at C0h address. Reserved 4 - The value read from this bit is indeterminate. Do not set this bit. 3 GF2 This bit is a general purpose user flag. * ...

Page 27

... Up to 64K byte external program memory if the internal program memory is disabled (EA = 0). • Programming and erase voltage with standard AT89C51RE2 features several on-chip memories: • Flash memory FM0: containing 128 Kbytes of program memory (user space) organized into 128 bytes pages. • ...

Page 28

... The lower 32K bank is used as common area for interrupt subrou- tines, bank switching and funtions calls between banks. The AT89C51RE2 also implements an extra upper 32K bank (Bank3) that allows exter- nal code execution. FCB ...

Page 29

Logical MCU Physical Flash Address Address FFFFh 0FFFFh upper 32K Bank 0 8000h 08000h 7FFFh 07FFFh 32K Common 0000h 00000h 7663B–8051–03/07 Figure 1. Program/Code Memory Organization EA=1 Logical MCU Physical Flash Address Address FFFFh 17FFFh upper 32K Bank 1 8000h ...

Page 30

... AT89C51RE2 30 When EA=0, the on-chip flash memory is disabled and the MCU core can address only up to 64kByte of external memory (none of the on-chip flash memory FM0 banks or RM0 can be mapped and executed). Figure 2. Program/Code Memory Organization EA=0 Logical MCU External Physical Memory Address Address ...

Page 31

On-Chip ROM bootloader Logical MCU Physical Logical MCU Address Address Address FFFFh 0FFFFh FFFFh Bank 0 8000h 08000h 8000h 7FFFh 07FFFh 0000h 00000h 7663B–8051–03/07 The On-chip ROM bootloader (RM0) is enable only for ISP operations after reset (boot- loader execution). ...

Page 32

... The BRV2-0 bits of the FSB (see Table 2 on page 9), the EA pin value upon reset and the presence of the external hardware conditions, allow to modify the default reset vec- tor of the AT89C51RE2. The Hardware conditions ( PSEN = 0) during the Reset falling edge force the on- chip bootloader execution. This allows an application to be built that will normally exe- cute the end user’ ...

Page 33

FM0 Memory Architecture User Space Extra Row (XRow or XAF) Hardware security Byte (HSB) 7663B–8051–03/07 The FM0 flash memory is made blocks: 1. The memory array (user space) 128K bytes 2. The Extra Row also called FM0 ...

Page 34

... Fuse Configuration Byte (FCB) AT89C51RE2 34 The Fuse configuration byte is a part of FM0. The 8 bits read/written by software (from FM0 or RM0) and written by hardware in paral- lel mode. Table 19. Fuse Configuration Byte (FCB Bit Bit Number Mnemonic Description X2 Mode Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset ...

Page 35

Column latches Cross Memory Access Description overview 1. N.A. Not applicable 7663B–8051–03/07 The column latches, also part of FM0, has a size of one page (128 bytes). The column latches are the entrance buffers of the three previous memory locations ...

Page 36

... Access and Operations Descriptions FM0 FLASH Registers BMSEL Register AT89C51RE2 36 The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA register. These registers are used to map the columns latche, HSB, FCB and extra row in the working data or code space. ...

Page 37

FCON Register 7663B–8051–03/07 Table 22. FCON Register FCON Register (S:D1h) Flash Control Register FPL3 FPL2 FPL1 Bit Bit Number Mnemonic Description Programming Launch Command Bits 7-4 FPL3:0 Write 5Xh followed by AXh to launch the programming according ...

Page 38

... FSTA Register AT89C51RE2 38 Table 23. FSTA Register FSTA Register (S:D3h) Flash Status Register FMR - - Bit Bit Number Mnemonic Description Flash Movc Redirection When code is executed from RM0 (and only RM0), this bit allow the MOVC instruction to be redirected to FM0. 7 FMR Clear this bit to allow MOVC instruction to read FM0 Set this bit to allow MOVC instruction to read RM0 This bit can be written only from RM0 (on-chip ROM bootloader execution) ...

Page 39

Mapping of the Memory Space 7663B–8051–03/07 By default, the user space is accessed by MOVC A, @A+DPTR instruction for read only. Setting FPS bit in FCON register takes precedence on the EXTRAM bit in AUXR register. The other memory spaces ...

Page 40

... Latches HSB FCB Reserved Reserved AT89C51RE2 40 FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the operation. This sequence is 5xh followed by Axh. Table 25 summarizes the memory spaces to program according to FMOD2:0 bits. ...

Page 41

Loading the Column Latches 7663B–8051–03/07 Any number of data from 0 byte to 128 bytes can be loaded in the column latches. The data written in the column latches can be written in a none consecutive order. The DPTR allows ...

Page 42

... Writting the Flash Spaces User AT89C51RE2 42 Figure 4. Column Latches Loading Procedure Note: The last page address used when loading the column latch is the one used to select the page programming address. Note: The value of MB02:0 during the last load gives the upper 32K bytes bank target selection ...

Page 43

Extra Row Hardware Security Byte (HSB) 7663B–8051–03/07 • Enable the interrupts. The following procedure is used to program the Extra Row space and is summarized in Figure 5: • Load data in the column latches from address FF80h to FFFFh. ...

Page 44

... Fuse Configuration Byte (FCB) AT89C51RE2 44 • Execute the MOVX @DPTR, A instruction. • Launch the programming by writing the data sequence 54h followed by A4h in FCON register. The end of the programming indicated by the FBusy flag cleared. • Restore the interrupts . Figure 6. Hardware Security Byte Programming Procedure ...

Page 45

Reset of columns latches space 7663B–8051–03/07 • Launch the programming by writing the data sequence 55h followed by A5h in FCON register. The end of the programming indicated by the FBusy flag cleared. • Restore the interrupts . Figure 7. ...

Page 46

... AT89C51RE2 46 In addition, the user application can reset the columns latches space manually. The following procedure is used to reset the columns latches space Launch the programming by writing the data sequence 53h followed by A3h in FCON register (from FM0 and RM0). 7663B–8051–03/07 ...

Page 47

Errors Report / Miscelaneous states Flash Busy flag Flash Programming Sequence Error Power Down Mode Request 7663B–8051–03/07 The FBUSY flag indicates on-going flash write operation. The busy flag is set by hardware, the hardware clears this flag after the end ...

Page 48

... Reading the Flash Spaces User Extra Row (XAF) Hardware Security Byte AT89C51RE2 48 The following procedure is used to read the User space: • Read one byte in Accumulator by executing MOVC A,@A+DPTR Note: FCON is supposed to be reset when not needed. Depending of the MBO2:0 bits, the MOVC A,@A+DPTR can address a specific upper 32K bytes bank ...

Page 49

Fuse ConfigurationByte 7663B–8051–03/07 Figure 9. HSB Reading Procedure The following procedure is used to read the Fuse Configuration byte and is sum- marized in Figure 9: • Map the FCB by writing 05h in FCON register. • Read the byte ...

Page 50

... Operation Cross Memory Access boot RM0 FM0 External memory BANK3 AT89C51RE2 50 Space addressable in read and write are: • RAM • ERAM (Expanded RAM access by movx) • XRAM (eXternal RAM) • FM0 ( user flash ) • Hardware byte • XROW FM0 • ...

Page 51

Sharing Instructions 7663B–8051–03/07 Table 27. Instructions shared Action RAM XRAM MOVX Read MOV A,@DPTR @A+DPTR MOVX Write MOV @DPTR,A Note using Column Latch Table 28. Write MOVX @DPTR,A FPS of FCCON Table 29. MOVC A, @A+DPTR executed ...

Page 52

... Flash Protection from Parallel Programming AT89C51RE2 52 The three lock bits in Hardware Security Byte (see "In-System Programming" section) are programmed according to Table 21 provide different level of protection for the on- chip flash memory FM0. They are set by default to level 4 Table 31. Program Lock Bit FLB2-0 ...

Page 53

... The bootloader manages a communication between a host platform running an ISP tool and a AT89C51RE2 target. The bootloader implemented in AT89C51RE2 is designed to reside in the dedicated ROM bank. This memory area can only be executed (fetched) when the processor enters the boot process. The implementation of the bootloader is based on standard set of libraries including INTEL hex based protocol, standard communication links and ATMEL ISP command set ...

Page 54

Bootloader Description Entry points Boot Process Description RESET EA=1 PSEN=0 Yes Communication link Hardware boot process request detection Communication link detection 7663B–8051–03/07 After reset only one bootloader entry point is possible. This entry point stands at address 0x0000 of the ...

Page 55

... Detection Start Interface 1 Yes Interface 2 Yes Notes Start of Frame (‘0’ = detected ; ‘1’ = not detected AT89C51RE2 implementation, Interface 1 refers to UART0 and Interface 2 refers to the OCD UART interface. Interface 2 Interface 1 Initialisation Initialisation Start Bootloader 7663B–8051–03/07 ...

Page 56

ISP Protocol Description Physical Layer Frame Description 7663B–8051–03/07 The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 1 bit • Flow control: none • Baud rate: autobaud is performed by ...

Page 57

... Sends frame (made of 2 ASCII characters per Byte) Echo analysis AT89C51RE2 40 An initialization step must be performed after each Reset. After microcontroller reset “ Performances” ...

Page 58

Each command flow may end with: • “X” checksum error • “L” read security is set • “P”: If program security is set • “.”: If command ok • byte + “.” : read byte ...

Page 59

... Reading/Blank checking memory Requests from Host Command Read selected memory Blank Check selected memory Answers from Bootloader Changing memory/page Requests from Host Answers from Bootloader AT89C51RE2 42 To start the reading or blank checking operation, Record Record Type Length Offset 04h 05h 0000h The boot loader can answer to a read command with: • ...

Page 60

Programming/Erasing memory Requests from Host Command Program selected memory Erase selected memory Answers from Bootloader Starting application Requests from Host 7663B–8051–03/07 Record Record Type Length Offset start 00h nb of data address 04h 05h 0000h The boot loader answers with: ...

Page 61

... ISP Commands description Select Memory Space AT89C51RE2 44 The ‘ command allows to route all read, write commands to a Select Memory Space’ selected area. For each area (Family) a code is defined. This code corresponds to the memory area encoded value in the INTEL HEX frame . ...

Page 62

Select Page 7663B–8051–03/07 The ‘ command allows to define a page number in the selected area. A page Select Page’ is defined as a 64K linear memory space (According to the INTEL HEX format). It doesn’t corresponds to a physical ...

Page 63

... Write commands FLASH CONFIGURATION SECURITY AT89C51RE2 46 The following table summarizes the memory spaces for which the write command can be applied. Table 28. Memory space & Select page Memory/Information Family FLASH SECURITY CONFIGURATION In case of write command to other area, nothing is done. The bootloader returns a Write protection (‘P’) if the SECURITY do not allow any write operation from the bootloader ...

Page 64

Erasing commands FLASH 7663B–8051–03/07 The erasing command is supported by the following areas : Table 32. Memory space & Erase Memory/Information Family FLASH Nothing is done on the other areas. The erasing command on the Flash memory: • erases the ...

Page 65

... Blank Checking commands FLASH AT89C51RE2 48 The blank checking command is supported by the following areas Table 33. Memory space & Erase Memory/Information Family FLASH Nothing is done on the other areas. The first not erased address is returned if the blank check is failed. The blank checking command on the Flash memory can be done from address 0000h to 1FFFFh ...

Page 66

Reading commands FLASH CONFIGURATION SECURITY BOOTLOADER SIGNATURE 7663B–8051–03/07 The reading command is supported by the following areas : Table 35. Memory space & Select page Memory/Information Family FLASH SECURITY CONFIGURATION BOOTLOADER SIGNATURE The reading command on the Flash memory can ...

Page 67

... Boot id2 Manuf. code Family code Product name Product rev AT89C51RE2 50 The start application command is used to quit the bootloader and start the application loaded. The start application is performed by a watchdog reset. The best way to start the application from a user defined entry point is to configure the FCB (Fuse Configuration Byte) before launching the watchdog ...

Page 68

Attempting an access with any other ‘coding’, ‘page number’ or ‘Address’ results in no action and no answer from the bootloader. 51 ...

Page 69

... Timer 0 AT89C51RE2 52 The AT89C51RE2 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. ...

Page 70

Mode 0 (13-bit Timer) Figure 7. Timer/Counter Mode 0 See the “Clock” section FTx ÷ 6 CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 1 (16-bit Timer) Figure 8. Timer/Counter x ...

Page 71

... FTx ÷ 6 CLOCK See the “Clock” section AT89C51RE2 54 Mode 2 configures Timer 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 9). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0 ...

Page 72

Timer 1 Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) Interrupt 7663B–8051–03/07 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The fol- ...

Page 73

... AT89C51RE2 56 Figure 11. Timer Interrupt System TF0 TCON.5 TF1 TCON.7 Timer 0 Interrupt Request ET0 IEN0.1 Timer 1 Interrupt Request ET1 IEN0.3 7663B–8051–03/07 ...

Page 74

Registers 7663B–8051–03/07 Table 40. TCON Register TCON (S:88h) Timer/Counter Control Register TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow Flag 7 TF1 Cleared by hardware when processor vectors to interrupt routine. Set by hardware ...

Page 75

... AT89C51RE2 58 Table 41. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control Bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. ...

Page 76

Table 42. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register – – – Bit Bit Number Mnemonic Description High Byte of Timer 0. 7:0 Reset Value = 0000 0000b Table 43. TL0 Register TL0 (S:8Ah) ...

Page 77

... AT89C51RE2 60 Table 45. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register – – – Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 1. Reset Value = 0000 0000b – – – – 0 – 7663B–8051–03/07 ...

Page 78

... Timer 2 Auto-Reload Mode 7663B–8051–03/07 The Timer 2 in the AT89C51RE2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by T2CON (Table 46) and T2MOD (Table 47) registers. Timer 2 operation is similar to Timer 0 and Timer 1.C/T2 selects F (timer operation) or external pin T2 (counter operation) as the timer clock input ...

Page 79

... Programmable Clock- Output AT89C51RE2 62 Figure 12. Auto-Reload Mode Up/Down Counter (DCEN = 1) F CLK PERIPH : 6 In the clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock gen- erator (See Figure 13). The input clock increments TL2 at frequency F timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2 ...

Page 80

Figure 13. Clock-Out Mode C/ FCLK PERIPH T2 T2EX TR2 T2CON 2 TL2 TH (8-bit) (8-bit) RCAP2L RCAP2H (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVER- FLOW TIMER 2 INTERRUPT 63 ...

Page 81

... Registers AT89C51RE2 64 Table 46. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1 ...

Page 82

Table 47. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...

Page 83

... Programmable Counter Array PCA AT89C51RE2 66 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules ...

Page 84

Figure 14. PCA Timer/Counter Fclk periph /6 Fclk periph / 2 T0 OVF P1.2 Idle 7663B–8051–03/ bit up/down counter CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 To PCA modules overflow It CL CMOD ECF ...

Page 85

... AT89C51RE2 68 Table 48. CMOD Register CMOD - PCA Counter Mode Register (D9h CIDL WDTE - Bit Bit Number Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. Watchdog Timer Enable ...

Page 86

Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can ...

Page 87

... Figure 15. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 AT89C51RE2 CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn.0 ECF PCA Modules: each one of the five compare/capture modules has six possible func- tions. It can perform: • 16-bit Capture, positive-edge triggered • ...

Page 88

Table 50 shows the CCAPMn settings for the various PCA functions. Table 50. CCAPMn Registers (n = 0-4) CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA ...

Page 89

... AT89C51RE2 72 Table 51. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 52 & ...

Page 90

Table 53. CCAPnL Registers (n = 0-4) CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L - ...

Page 91

... Cex.n ECOMn 16-bit Software Timer/ Compare Mode AT89C51RE2 74 To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the mod- ule (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH) ...

Page 92

Figure 17. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable 1 0 High Speed Output Mode 7663B–8051–03/07 CF CCF4 CR CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn ...

Page 93

... Figure 18. PCA High Speed Output Mode Write to Reset CCA PnL Write to CCAPnH 0 1 Enable Pulse Width Modulator Mode AT89C51RE2 CCF4 CCF3 CCF2 CCF1 CCF0 CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECO Mn CAPPn CAPNn MATn TOGn PWMn ECCFn Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’ ...

Page 94

PCA Watchdog Timer 7663B–8051–03/07 Figure 19. PCA PWM Mode Overflow Enable ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers ...

Page 95

... Serial I/O Port Framing Error Detection AT89C51RE2 78 The serial I/O ports in the AT89C51RE2 are compatible with the serial I/O port in the 80C52. They provide both synchronous and asynchronous communication modes. They oper- ates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simul- ...

Page 96

Automatic Address Recognition Given Address 7663B–8051–03/07 Figure 22. UART Timings in Mode 1 RXD Start bit RI SMOD0=X FE SMOD0=1 Figure 23. UART Timings in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0=0 RI ...

Page 97

... Broadcast Address Reset Addresses AT89C51RE2 80 The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. ...

Page 98

Registers 7663B–8051–03/07 Table 56. SADEN_0 Register SADEN - Slave Address Mask Register UART 0(B9h Reset Value = 0000 0000b Not bit addressable Table 57. SADDR_0 Register SADDR - Slave Address Register UART 0(A9h Reset ...

Page 99

... Baud Rate Selection for UART 0 for Mode 1 and 3 AT89C51RE2 82 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON_0 registers. Figure 24. Baud Rate Selection for UART 0 TIMER1 TIMER_BRG_RX 0 TIMER2 1 RCLK INT_BRG TIMER1 TIMER_BRG_TX 0 TIMER2 ...

Page 100

Baud Rate Selection for UART 1 for Mode 1 and 3 7663B–8051–03/07 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON_1 registers. Figure 25. Baud Rate Selection for UART 1 TIMER1 ...

Page 101

... BRR_1 AT89C51RE2 84 The AT89C51RE2 implements two internal baudrate generators. Each one is dedicated to the coresponding UART. The configuration and operating mode for both BRG are similar. When an internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL (BRL or BRL_1 registers) reload value, the value of SPD (or SPD_1) bit (Speed Mode) in BDRCON (BDRCON_1) register and the value of the SMOD1 bit in PCON register ...

Page 102

Table 62. SCON_0 register SCON_0 - Serial Control Register for UART 0(98h FE/SM0_0 SM1_0 SM2_0 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop ...

Page 103

... AT89C51RE2 86 Table 63. SCON_1 Register SCON_1 - Serial Control Register for UART 1(90h FE/SM0_1 SM1_1 SM2_1 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. FE_1 Set by hardware when an invalid stop bit is detected. ...

Page 104

UART Registers 7663B–8051–03/07 Table 64. Example of Computed Value When X2=1, SMOD1=1, SPD=1 Baud Rates F = 16. 384 MHz OSC BRL 115200 247 57600 238 38400 229 28800 220 19200 203 9600 149 4800 43 Table 65. Example of ...

Page 105

... AT89C51RE2 88 Table 68. SBUF_1 Register SBUF - Serial Buffer Register for UART 1(C1h Reset Value = XXXX XXXXb Table 69. BRL_1 Register BRL - Baud Rate Reload Register for the internal baud rate generator 1 (BBh Reset Value = 0000 0000b 7663B–8051–03/07 ...

Page 106

Table 70. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow, ...

Page 107

... AT89C51RE2 90 Table 71. PCON Register PCON - Power Control Register (87h SMOD1_0 SMOD0_0 - Bit Bit Number Mnemonic Serial port Mode bit 1 for UART 7 SMOD1_0 Set to select double baud rate in mode Serial port Mode bit 0 for UART 6 SMOD0_0 Cleared to select SM0 bit in SCON register. ...

Page 108

Table 72. BDRCON_0 Register BDRCON_0 - Baud Rate Control Register (9Bh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit Reserved ...

Page 109

... AT89C51RE2 92 Table 73. BDRCON_1 Register BDRCON - Baud Rate Control Register (BCh SMOD1_1 SMOD0_1 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 for UART 1 7 SMOD1_1 Set to select double baud rate in mode Serial port Mode bit 0 for UART 1 6 SMOD0_1 Cleared to select SM0 bit in SCON register ...

Page 110

... Individual Enable 7663B–8051–03/07 The AT89C51RE2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), two serial ports interrupts, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 28 ...

Page 111

... Registers AT89C51RE2 94 Table 74. Priority Level Bit Values IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced ...

Page 112

Table 75. IEN0 Register IEN0 - Interrupt Enable Register (A8h ET2 Bit Bit Number Mnemonic Description Enable All interrupt bit 7 EA Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt ...

Page 113

... AT89C51RE2 96 Table 76. IPL0 Register IPL0 - Interrupt Priority Register (B8h PPCL PT2L Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority bit 6 PPCL Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit ...

Page 114

Table 77. IPH0 Register IPH0 - Interrupt Priority High Register (B7h PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA ...

Page 115

... AT89C51RE2 98 Table 78. IEN1 Register IEN1 - Interrupt Enable Register (B1h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved Serial port 1 Enable bit 3 ES_1 Cleared to disable serial port interrupt. Set to enable serial port interrupt. SPI interrupt Enable bit Cleared to disable SPI interrupt. ...

Page 116

Table 79. IPL1 Register IPL1 - Interrupt Priority Register (B2h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 ...

Page 117

... AT89C51RE2 100 Table 80. IPH1 Register IPH1 - Interrupt Priority High Register (B3h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. ...

Page 118

Interrupt Sources and Vector Addresses 7663B–8051–03/07 Table 81. Interrupt Sources and Vector Addresses Number Polling Priority Interrupt Source Keyboard ...

Page 119

... Idle mode. The contents of the status of the Port pins during Idle mode is detailed in Table 82. To enter Idle mode, set the IDL bit in PCON register (see Table 83). The AT89C51RE2 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed ...

Page 120

... Take care, however, that VDD is not reduced until Power-Down mode is invoked. To enter Power-Down mode, set PD bit in PCON register. The AT89C51RE2 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. ...

Page 121

... AT89C51RE2 104 pins, the instruction immediately following the instruction that activated the Power-Down mode should not write to a Port pin or to the external RAM. Note: Exit from power-down by reset redefines all the RAM content. Table 82. Pin Conditions in Special Operating Modes Mode ...

Page 122

Registers 7663B–8051–03/07 Table 83. PCON Register PCON (87:h) Power configuration Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial Port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...

Page 123

... Oscillator Registers AT89C51RE2 106 To optimize the power consumption and execution time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the CPU and peripherals. Table 84. CKRL Register CKRL – Clock Reload Register (97h CKRL7 CKRL6 ...

Page 124

Functional Block Diagram Figure 30. Functional Oscillator Block Diagram Reset F Xtal1 OSC Osc Xtal2 :2 Prescaler Divider 7663B–8051–03/07 Reset Value = 00X1 0000b Not bit addressable Reload CKRL 1 8-bit 0 Prescaler-Divider X2 CKCON0 • A hardware RESET puts ...

Page 125

... Hardware Watchdog Timer Using the WDT AT89C51RE2 108 The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H ...

Page 126

... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51RE2 while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. ...

Page 127

... Reduced EMI Mode AT89C51RE2 110 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches ...

Page 128

... Interrupt Power Reduction Mode 7663B–8051–03/07 The AT89C51RE2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power down modes. ...

Page 129

... Registers AT89C51RE2 112 Table 89. KBF Register KBF-Keyboard Flag Register (9Eh KBF7 KBF6 KBF5 Bit Bit Number Mnemonic Description Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a 7 KBF7 Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set. ...

Page 130

Table 90. KBE Register KBE-Keyboard Input Enable Register (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard line 7 Enable bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable KBF. 7 bit ...

Page 131

... AT89C51RE2 114 Table 91. KBLS Register KBLS-Keyboard Level Selector Register (9Ch KBLS7 KBLS6 KBLS5 Bit Bit Number Mnemonic Description Keyboard line 7 Level Selection bit 7 KBLS7 Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. Keyboard line 6 Level Selection bit ...

Page 132

Serial Port Interface (SPI) Features Signal Description Master Output Slave Input (MOSI) Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) 7663B–8051–03/07 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and ...

Page 133

... Baud Rate AT89C51RE2 116 In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. ...

Page 134

Functional Description Figure 34. SPI Module Block Diagram SPSCR SPIF - OVR SPI Control SPCON SPR2 SPEN SSDIS Operating Modes 7663B–8051–03/07 Figure 34 shows a detailed structure of the SPI Module. Internal Bus UARTM SPTEIE MODFIE MODF SPTE MSTR CPOL ...

Page 135

... Master Mode Slave Mode Transmission Formats AT89C51RE2 118 When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 35) ...

Page 136

Figure 36. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 37. Data Transmission Format (CPHA = 1) ...

Page 137

... MISO Data Byte 1 BYTE 1 under transmission SPTE AT89C51RE2 120 When a transmission is in progress a new data can be queued and sent as soon as transmission has been completed possible to transmit bytes without latency, useful in some applications. The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that the user application can write SPDAT with the data to be transmitted until the SPTE becomes cleared ...

Page 138

Error Conditions Mode Fault Error (MODF) 7663B–8051–03/07 The following flags in the SPSCR register indicate the SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the ...

Page 139

... OverRun Condition Interrupts AT89C51RE2 122 Figure 41. Mode Fault Conditions in Slave Mode 0 SCK cycle # 1 SCK z 0 (from master) 1 MOSI z (from master MISO MSB z (from slave (slave) 0 MODF detected Note: when SS is discarded (SS disabled not possible to detect a MODF error in slave mode because the SPI is internally selected ...

Page 140

Registers Serial Peripheral Control Register (SPCON) 7663B–8051–03/07 Figure 42. SPI Interrupt Requests Generation SPIF SPTEIE SPTE MODFIE MODF Three registers in the SPI module provide control, status and data storage functions. These registers are describe in the following paragraphs. • ...

Page 141

... Serial Peripheral Status Register and Control (SPSCR) AT89C51RE2 124 Bit Number Bit Mnemonic Description Clock Polarity 3 CPOL Cleared to have the SCK set to ’0’ in idle state. Set to have the SCK set to ’1’ in idle state. Clock Phase Cleared to have the data sampled when the SCK leaves the idle ...

Page 142

Serial Peripheral DATa Register (SPDAT) 7663B–8051–03/07 Bit Bit Number Mnemonic Description Mode Fault - Set by hardware to indicate that the SS pin is in inappropriate logic level (in both master and slave modes). - Cleared by hardware when reading ...

Page 143

... AT89C51RE2 126 SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken when writing to them while a transmission is on-going: • Do not change SPR2, SPR1 and SPR0 • Do not change CPHA and CPOL • ...

Page 144

... This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51RE2 is powered up. In order to startup and maintain the microcontroller in correct operating mode stabilized in the V ...

Page 145

... Figure 44. Power Fail Detect Vcc Reset Vcc AT89C51RE2 128 The Power fail detect monitor the supply generated by the voltage regulator and gener- ate a reset if this supply falls below a safety threshold as illustrated in the Figure 44 below. When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input ...

Page 146

Power-off Flag 7663B–8051–03/07 The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced still applied to the device and could ...

Page 147

... The Reset input can be used to force a reset pulse longer than the internal reset con- trolled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V value and input characteristics are discussed in the Section “DC Characteristics” of the AT89C51RE2 datasheet. Figure 46. Reset Circuitry and Power-On Reset RST VSS a ...

Page 148

Reset Output 7663B–8051–03/07 As detailed in Section “Hardware Watchdog Timer”, page 108, the WDT generates a 96- clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of ...

Page 149

... Input High Voltage RST, XTAL1 IH1 V Output Low Voltage, ports Output Low Voltage, port 0, ALE, PSEN OL1 V Output High Voltage, ports Output High Voltage, port 0, ALE, PSEN OH1 AT89C51RE2 132 Note: + 0.5V CC (2) =2.7V to 5.5V MHz Min Typ -0.5 0 0.9 CC 0.7 V ...

Page 150

T = -40°C to +85° 0V Symbol Parameter R RST Pull-down Resistor RST I Logical 0 Input Current ports and Input Leakage Current LI I Logical 1 ...

Page 151

... AC Parameters Explanation of the AC Symbols AT89C51RE2 134 Figure 49. I Test Condition, Idle Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Figure 50. I Test Condition, Power-down Mode RST EA (NC) XTAL2 XTAL1 V SS Figure 51. Clock Signal Waveform for ...

Page 152

External Program Memory Characteristics 7663B–8051–03/07 Table 99, Table 100 and Table 106 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value in the correponding column (-M ...

Page 153

... AT89C51RE2 136 Table 100. AC Parameters for a Variable Clock Standard Symbol Type Clock T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min LLPL T Min PLPH T Max PLIV T Min x PXIX T Max PXIZ T Max AVIV ...

Page 154

External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 External Data Memory Characteristics 7663B–8051–03/ LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T TPLAZ AVLL PXIX ...

Page 155

... AT89C51RE2 138 Table 102. AC Parameters for a Fix Clock -M Symbol Min T 125 RLRH T 125 WLWH T RLDV T 0 RHDX T RHDZ T LLDV T AVDV T 45 LLWL T 70 AVWL T 5 QVWX T 155 QVWH T 10 WHQX T 0 RLAZ T 5 WHLH Table 103. AC Parameters for a Variable Clock Standard ...

Page 156

External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode 7663B–8051–03/07 T LLWL ...

Page 157

... Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Waveforms AT89C51RE2 140 Table 105. AC Parameters for a Fix Clock -M Symbol Min T 300 XLXL T 200 QVHX T 30 XHQX T 0 XHDX T XHDV Table 106. AC Parameters for a Variable Clock ...

Page 158

AC Testing Input/Output Waveforms Float Waveforms Clock Waveforms 7663B–8051–03/07 V -0.5V CC INPUT/OUTPUT 0.45V AC inputs during testing are driven at V Timing measurement are made 0. 0.1V OL For timing purposes as ...

Page 159

... This propagation delay is dependent on variables such as temperature and pin loading. Propaga- tion also varies from output to output and component. Typically though (T delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. AT89C51RE2 142 STATE5 STATE6 ...

Page 160

Flash Memory 7663B–8051–03/07 Table 107. Timing Symbol Definitions Signals S (Hardware PSEN#,EA condition) R RST B FBUSY flag Table 108. Memory AC Timing VDD = 3V to 5.5V -40 to +85°C Symbol Parameter T Input PSEN# Valid to ...

Page 161

... Ordering Information AT89C51RE2 144 Table 109. Possible Order Entries Part Number Supply Voltage AT89C51RE2-SLSUM AT89C51RE2-RLTUM AT89C51RE2-SLSEM AT89C51RE2-RLTEM Temperature Range 2.7V-5.5V Industrial 2.7V-5.5V Engineering Samples Package PLCC44 VQFP44 PLCC44 VQFP44 7663B–8051–03/07 ...

Page 162

Packaging Information PLCC44 7663B–8051–03/07 145 ...

Page 163

... VQFP44 AT89C51RE2 146 7663B–8051–03/07 ...

Page 164

... Flash memory organization ................................................................................ 27 ............................................................................................................................ 28 Flash Operations ................................................................................................ 28 Flash Registers and Memory Map...................................................................... 30 Bootloader Architecture .................................................................... 36 Introduction ......................................................................................................... 36 Bootloader Description ....................................................................................... 37 ISP Protocol Description..................................................................................... 39 Protocol............................................................................................................... 40 ISP Commands description ................................................................................ 44 Timers/Counters ................................................................................. 52 Timer/Counter Operations .................................................................................. 52 Timer 0................................................................................................................ 52 Timer 1................................................................................................................ 55 Interrupt .............................................................................................................. 55 Registers............................................................................................................. 57 Timer 2 ................................................................................................. 61 Auto-Reload Mode.............................................................................................. 61 Programmable Clock-Output .............................................................................. 62 Registers............................................................................................................. 64 7663B–8051–03/07 AT89C51RE2 1 ...

Page 165

... Using the WDT ................................................................................................. 108 WDT During Power Down and Idle................................................................... 109 Reduced EMI Mode ........................................................................... 110 Keyboard Interface ........................................................................... 111 Registers........................................................................................................... 112 Serial Port Interface (SPI) ................................................................ 115 Features............................................................................................................ 115 Signal Description............................................................................................. 115 Functional Description ...................................................................................... 117 Power Monitor ................................................................................... 127 Description........................................................................................................ 127 AT89C51RE2 2 7663B–8051–03/07 ...

Page 166

... Power-off Flag ................................................................................... 129 Reset .................................................................................................. 130 Introduction ....................................................................................................... 130 Reset Input ....................................................................................................... 130 Reset Output .....................................................................................................131 Electrical Characteristics ................................................................. 132 Absolute Maximum Ratings ..............................................................................132 DC Parameters .................................................................................................132 AC Parameters ................................................................................................. 134 Ordering Information ........................................................................ 144 Packaging Information ..................................................................... 145 PLCC44 ............................................................................................................ 145 VQFP44 ............................................................................................................ 146 7663B–8051–03/07 AT89C51RE2 3 ...

Page 167

... Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for useas components in applications intended to support or sustainlife. ©2007 Atmel Corporation. All rights reserved. Atmel tered trademarks, of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...

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