at89c5131 ATMEL Corporation, at89c5131 Datasheet - Page 134

• Manufacturer Part Number: at89c5131
• Description: 8-bit Flash Microcontroller With Full Speed Usb Device At89c5131
• Manufacturer: ATMEL Corporation

USB Interrupt Control System
132
AT89C5131
Table 89. Priority Levels
As shown in Figure 68, many events can produce a USB interrupt:
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•
•
•
•
•
•
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TXCMPL: Transmitted In Data (see Table 96 on page 139). This bit is set by
hardware when the Host accept a In packet.
RXOUTB0: Received Out Data Bank 0 (see Table 96 on page 139). This bit is set
by hardware when an Out packet is accepted by the endpoint and stored in bank 0.
RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (see Table 96
on page 139). This bit is set by hardware when an Out packet is accepted by the
endpoint and stored in bank 1.
RXSETUP: Received Setup (see Table 96 on page 139). This bit is set by hardware
when an SETUP packet is accepted by the endpoint.
STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (see Table 96
on page 139). This bit is set by hardware when a STALL handshake has been sent
as requested by STALLRQ, and is reset by hardware when a SETUP packet is
received.
SOFINT: Start of Frame Interrupt (See “USBIEN Register USBIEN (S:BEh) USB
Global Interrupt Enable Register” on page 136). This bit is set by hardware when a
USB Start of Frame packet has been received.
WUPCPU: Wake-Up CPU Interrupt (See “USBIEN Register USBIEN (S:BEh) USB
Global Interrupt Enable Register” on page 136). This bit is set by hardware when a
USB resume is detected on the USB bus, after a SUSPEND state.
SPINT: Suspend Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global
Interrupt Enable Register” on page 136). This bit is set by hardware when a USB
suspend is detected on the USB bus.
IPHUSB
0
0
1
1
IPLUSB
0
1
0
1
USB Priority Level
0
1
2
3
Lowest
Highest
4136C–USB–04/05