at89c5131 ATMEL Corporation, at89c5131 Datasheet - Page 144
at89c5131
Manufacturer Part Number
at89c5131
Description
8-bit Flash Microcontroller With Full Speed Usb Device At89c5131
Manufacturer
ATMEL Corporation
Datasheet
1.AT89C5131.pdf
(176 pages)
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142
AT89C5131
Table 100. UEPRST Register
UEPRST (S:D5h)
USB Endpoint FIFO Reset Register
Reset Value = 00h
Bit Number
7
-
7
6
5
4
3
2
1
0
Mnemonic Description
EP6RST
EP6RST
EP5RST
EP4RST
EP3RST
EP2RST
EP1RST
EP0RST
Bit
6
-
Reserved
The value read from this bit is always 0. Do not set this bit.
Endpoint 6 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 5 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 4 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 3 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 2 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 1 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
Endpoint 0 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
EP5RST
5
EP4RST
4
EP3RST
3
EP2RST
2
EP1RST
1
4136C–USB–04/05
EP0RST
0