at89lp2052-20xi ATMEL Corporation, at89lp2052-20xi Datasheet
at89lp2052-20xi
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at89lp2052-20xi Summary of contents
Page 1
... CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch required 6 clock cycles, forc- ing instructions to execute in 12 clock cycles. In the AT89LP2052/LP4052 CPU, instructions need only clock cycles providing times more through- put than the standard 8051 ...
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... In addition both timer/counters may be configured as 8-bit Pulse Width Modulators with 8-bit prescalers. The I/O ports of the AT89LP2052/LP4052 can be independently configured in one of four oper- ating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the ports are tri-stated. Push-pull output mode provides full CMOS drivers and open-drain mode provides just a pull-down ...
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... MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured I/O as slave, this pin is an output. P1.7: User-configurable I/O Port 1 bit 7. I/O 19 P1.7 SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is I/O an input. 20 VCC I Supply Voltage 3547H–MICRO–5/07 AT89LP2052/LP4052 3 ...
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... Configurable I/O 5. Memory Organization The AT89LP2052/LP4052 uses a Harvard Architecture with separate address spaces for pro- gram and data memory. The program memory has a regular linear address space with support for up to 64K bytes of directly addressable application code. The data memory has 256 bytes of internal RAM which is divided into regions that may be accessed by different instruction classes ...
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... Figure 5-1. 5.2 Data Memory The AT89LP2052/LP4052 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O memory. The lower 128 bytes of data memory may be accessed through both direct and indirect addressing. The upper 128 bytes of data memory and the 128 bytes of I/O memory share the same address space (see be accessed using indirect addressing ...
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... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 6-1. AT89LP2052/LP4052 SFR Map and Reset Values 0F8H 0F0H B* ...
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... Comparison to Standard 8051 The AT89LP2052/LP4052 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assign- ments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are differ- ent from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051 ...
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... Enhanced CPU The AT89LP2052/LP4052 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2-mode 8051 devices). The increase in performance is due to two factors ...
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... Single-cycle ALU Operation (Example: INC R0) System Clock Total Execution Time ALU Operation Execute Result Write Back Fetch Next Instruction Two-Cycle ALU Operation (Example: ADD A, System Clock Total Execution Time ALU Operation Execute Result Write Back Fetch Next Instruction AT89LP2052/LP4052 #data ...
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... AT89LP2052 and 4K bytes for the AT89LP4052. This should be the responsi- bility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89LP2052 (with 2K bytes of memory), whereas LJMP 900H would not ...
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... Figures 11-2 and 11-3 C1 ± for Crystals = 5 pF ± for Ceramic Resonators Quartz Crystal Clock Input 6.5 6 5.5 5 4.5 4 3.5 3 2 Frequency (MHz) AT89LP2052/LP4052 Figure 11-1. Either a quartz crystal or illustrate the relationship between sam ...
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... Figure 11-3. Ceramic Resonator Clock Source To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 11-4. External Clock Drive Configuration AT89LP2052/LP4052 12 Ceramic Resonator Clock Input Frequency (MHz) Figure 11- ...
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... Reset During reset, all I/O Registers are set to their initial values, the port pins are tri-stated, and the program starts execution from the Reset Vector, 0000H. The AT89LP2052/LP4052 has four sources of reset: power-on reset, brown-out reset, external reset, and watchdog reset. 12.1 Power-on Reset A Power-on Reset (POR) is generated by an on-chip detection circuit ...
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... The RST pin must be held high for longer than the time-out period to ensure that the device is reset properly. The device will begin execut- ing once RST is brought back low. AT89LP2052/LP4052 14 has been reduced. Power-down CC 3547H– ...
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... Idle Mode bit. Setting this bit activates Idle mode operation 14. Interrupts The AT89LP2052/LP4052 provides 6 interrupt sources: two external interrupts, two timer inter- rupts, a serial port interrupt, and an analog comparator interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space. ...
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... In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new. AT89LP2052/LP4052 16 Interrupt Vector Addresses ...
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... Figure 14-1. Minimum Interrupt Response Time Figure 14-2. Maximum Interrupt Response Time 3547H–MICRO–5/07 Figures 14-1 and 14-2. Clock Cycles 1 INT0 IE0 Ack. Instruction Cur. Instr. LCALL Clock Cycles 1 INT0 IE0 Instruction RETI AT89LP2052/LP4052 5 1st ISR Instr. 13 Ack. 4 Cyc. Instr. LCALL 1st ISR In 17 ...
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... Symbol Function PC Comparator Interrupt Priority Low PS Serial Port Interrupt Priority Low PT1 Timer 1 Interrupt Priority Low PX1 External Interrupt 1 Priority Low PT0 Timer 0 Interrupt Priority Low PX0 External Interrupt 0 Priority Low AT89LP2052/LP4052 18 – ES ET1 – PS PT1 Reset Value = 00X0 0000B ...
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... PX0H External Interrupt 0 Priority High 15. I/O Ports All 15 port pins on the AT89LP2052/LP4052 may be configured to one of four modes: quasi-bidi- rectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may be assigned in software on a pin-by-pin basis as shown in default to input-only mode after reset. Each port pin also has a Schmitt-triggered input for improved input noise rejection ...
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... The quasi-bidirectional port configuration is shown in circuitry of P3.2 and P3.3 is not disabled during Power-down (see Figure 15-1. Quasi-bidirectional Output 15.2 Input-only Mode The input port configuration is shown in input noise rejection. Figure 15-2. Input Only Figure 15-3. Input Only for P3.2 and P3.3 AT89LP2052/LP4052 20 1 Clock Delay (D Flip-Flop) From Port Register Input Data Figure 15-2 ...
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... Port 1 Analog Functions The AT89LP2052/LP4052 incorporates an analog comparator. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both the digital outputs and digital inputs disabled. Digital outputs are disabled by put- ting the port pins into the input-only mode as described in Digital inputs on P1 ...
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... SETB PX.Y 15.7 Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP2052/LP4052 share functionality with the various I/Os needed for the peripheral units. pins. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, oth- erwise, the input/output will always be “ ...
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... P3.4 P3.5 P3.6 16. Enhanced Timer/Counters The AT89LP2052/LP4052 has two 16-bit Timer/Counter registers: Timer 0 and Timer Timer, the register is incremented every clock cycle. Thus, the register counts clock cycles. Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency Counter, the register is incremented in response to a 1-to-0 transition at its corresponding input pin ...
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... RH1/RL1 and the over- flow flag bit in TCON is set. See the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the same for Timer/Counter 0. Figure 16-2. Timer/Counter 1 Mode 1: 16-bit Auto-Reload INT1 Pin AT89LP2052/LP4052 24 OSC C C Pin ...
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... Timer 1. Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP2052/LP4052 can appear to have three Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...
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... CPU vectors to the interrupt routine. When IT0 is cleared, IE0 is sampled and inverted from the external interrupt pin. The flag will be set or cleared by hardware depending on the state of P3.2. IT0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. AT89LP2052/LP4052 26 TF0 TR0 ...
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... Control Mode Timer 0 low-byte Timer 1 low-byte Timer 0 high-byte Timer 1 high-byte Mode Timer 0 reload low-byte Timer 1 reload low-byte Timer 0 reload high-byte Timer 1 reload high-byte AT89LP2052/LP4052 Reset Value = 0000 0000B C Timer0 Timer 0 gate bit Timer 0 counter/timer select bit Timer 0 M1 bit ...
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... The PWM will only function if the timer is in Mode 0 or Mode 1. In Mode 0, TL0 acts as a logarith- mic prescaler driving TH0 (see value. In Mode 1, TL0 provides linear prescaling with an 8-bit auto-reload from RL0 (see 16-7). Figure 16-5. Asymmetrical Pulse Width Modulation AT89LP2052/LP4052 28 PSC12 PSC11 PSC10 ...
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... INTx pin. If ITx = 1, external interrupt x is nega- tive edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle 3547H–MICRO–5/07 OSC Control TR1 GATE INT1 Pin OSC Control TR1 GATE INT1 Pin AT89LP2052/LP4052 RH1 (8 Bits) TL1 OCR1 (8 Bits) = PSC1 TH1 (8 Bits) RH1 (8 Bits) RL1 ...
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... The port can be programmed such that when the stop bit is received, the serial port interrupt is activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. The following example shows how to use the serial interrupt for multiprocessor communications. When the master processor must transmit a block of data to one of several slaves, it first sends AT89LP2052/LP4052 30 3547H–MICRO–5/07 ...
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... SM2 REN TB8 5 4 SM1 Mode Description 0 0 shift register 1 1 8-bit UART 0 2 9-bit UART 1 3 9-bit UART AT89LP2052/LP4052 Reset Value = 0000 0000B RB8 (2) Baud Rate f /2 osc variable f / /16 osc osc variable ...
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... Programmers can achieve very low baud rates with Timer 1 by configuring the Timer to run as a 16-bit auto-reload timer (high nibble of TMOD = 0001B). In this case, the baud rate is given by the following formula. AT89LP2052/LP4052 32 Oscillator Frequency Mode 0 Baud Rate ...
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... Timer 1. Commonly Used Baud Rates Generated by Timer 1 f (MHz) OSC 11.059 9.6K 11.059 4.8K 11.059 2.4K 11.059 1.2K 11.059 137.5 11.986 110 6 110 12 AT89LP2052/LP4052 Timer 1 SMOD1 C/T Mode ...
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... Figure 18-1. Serial Port Mode 0 1/2 f osc WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) AT89LP2052/LP4052 34 INTERNAL BUS “1“ INTERNAL BUS 3547H–MICRO–5/07 ...
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... Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the AT89LP2052/LP4052, the baud rate is determined by the Timer 1 overflow rate. The baud rate is determined by the Timer 1 overflow rate. ...
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... DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 TXD START BIT TI ÷16 RESET RX CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI AT89LP2052/LP4052 36 INTERNAL BUS “1” SBUF CL ZERO DETECTOR SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI TI SERIAL PORT ÷ ...
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... RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. 3547H–MICRO–5/07 show a functional diagram of the serial port in Modes 2 and 3. The and Either SM2 = 0 or the received 9th data bit = 1 AT89LP2052/LP4052 37 ...
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... Figure 18-3. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 AT89LP2052/LP4052 38 INTERNAL BUS INTERNAL BUS 3547H–MICRO–5/07 ...
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... RX CLOCK SEND TI SERIAL PORT ÷16 LOAD RX CLOCK RI SBUF START RX CONTROL SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) LOAD SBUF SBUF READ SBUF INTERNAL BUS AT89LP2052/LP4052 TXD SHIFT D6 D7 TB8 STOP BIT RB8 STOP BIT 39 ...
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... A unique address for slave 1 would be 1100 0001 since a “1” in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit (for slave 0) and bit (for slave 1). Thus, both could be addressed with 1100 0000. AT89LP2052/LP4052 40 SADDR = 1100 0000 ...
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... UART drivers which do not make use of this feature. 19. Serial Peripheral Interface The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the AT89LP2052/LP4052 and peripheral devices or between multiple AT89LP2052/LP4052 devices. The AT89LP2052/LP4052 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • ...
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... In slave mode, SS must be driven low to select an individual device as a slave. When SS is driven high, the slave’s SPI port is deacti- vated and the MOSI/P1.5 pin can be used as a general-purpose input. Figure 19-1. SPI Master-Slave Interconnection Figure 19-2. SPI Block Diagram AT89LP2052/LP4052 42 MSB Master LSB ...
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... WCOL, and continues trans- mission without stopping and restarting the clock generator. As long as the CPU can keep the write buffer full in this manner, multiple bytes may be transferred with minimal latency between bytes. 3547H–MICRO–5/07 AT89LP2052/LP4052 43 ...
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... Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE. 2. Enable the master SPI prior to the slave device. 3. Slave echoes master on the next Tx if not loaded with new data. AT89LP2052/LP4052 44 DORD ...
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... Not Bit Addressable SPD7 SPD6 Bit 7 6 3547H–MICRO–5/07 LDEN – – SPD5 SPD4 SPD3 AT89LP2052/LP4052 Reset Value = 000X X000B – DISSO ENH Reset Value = 00H (after cold reset) unchanged (after warm reset) SPD2 SPD1 SPD0 ...
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... SCK phase and polarity with respect to the serial data. CPHA and CPOL determine which format is used for transmission. The SPI data transfer formats are shown in Figures 19-4 and CPOL, and SPR should be set up before the interface is enabled, and the master device should be enabled before the slave device(s). AT89LP2052/LP4052 46 7 Serial Master 8 ...
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... Master and Slave mode without reconfiguring the pins. 3547H–MICRO–5/ MSB MSB 22. When the SPI is in Master mode, SCK and MOSI must be configured as AT89LP2052/LP4052 LSB LSB Section 15.7 “Port Alternate Func- 47 ...
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... Analog Comparator A single analog comparator is provided on the AT89LP2052/LP4052. Comparator operation is such that the output is a logic “1” when the positive input AIN0 (P1.0) is greater than the negative input AIN1 (P1.1). Otherwise, the output is a zero. Setting the CEN bit in ACSR enables the comparator. When the comparator is first enabled, the comparator output and interrupt flag are guaranteed to be stable only after 10 µ ...
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... Positive edge Toggle with debounce Positive edge with debounce Negative edge Toggle Negative edge with debounce Positive (High) level 3547H–MICRO–5/07 CIDL CF CEN AT89LP2052/LP4052 Reset Value = XXX0 0000B CM2 CM1 CM0 ...
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... WDTRST register and then 1EH to the WDTRST register. An incorrect feed or enable sequence will cause an immediate watchdog reset. The program sequence to feed or enable the watchdog timer is as follows: AT89LP2052/LP4052 50 Watchdog Timer Time-out Period Selection WDT Prescaler Bits ...
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... The AT89LP2052/LP4052 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP2052/LP4052 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP2052/LP4052 may take clock cycles to complete. The execution times of most instructions may be computed using Table 22-1 ...
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... SUBB A, direct SUBB A, @Ri SUBB A, #data INC Rn INC direct INC @Ri INC A DEC Rn DEC direct DEC @Ri DEC A INC DPTR MUL AB DIV AT89LP2052/LP4052 52 Generic Instruction Execution Times and Exceptions Detailed Arithmetic Instruction Summary Bytes Cycle Count # bytes # bytes + 1 Clock Cycles 8051 LP2052 ...
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... ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data RL A RLC RRC A SWAP A 3547H–MICRO–5/07 Detailed Logical Instruction Summary Bytes AT89LP2052/LP4052 Clock Cycles 8051 LP2052 ...
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... MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri AT89LP2052/LP4052 54 Detailed Data Transfer Instruction Summary Bytes Clock Cycles 8051 LP2052 ...
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... JMP @A+DPTR CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP 3547H–MICRO–5/07 Detailed Bit Instruction Summary Bytes Detailed Branching Instruction Summary Bytes AT89LP2052/LP4052 Clock Cycles 8051 LP2052 ...
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... Device # AT89LP2052 AT89LP4052 The AT89LP2052/LP4052 provides two flexible interfaces for programming the Flash memory: a parallel interface which uses 10 pins; and a serial interface which uses the 4 SPI pins. The par- allel and serial programming algorithms are identical. Both interfaces support the same command format where each command is issued to the device one byte at a time ...
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... Bit 3 System Clock Out *The AT89LP2052/LP4052 has ISP enabled by default from the factory. However, if ISP is later disabled, the ISP Enable Fuse must be enabled by using Parallel Programming before entering ISP mode. When disabling the ISP fuse during ISP, the current ISP session will remain active until RST is brought low. ...
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... DATA Polling The AT89LP2052/LP4052 implements DATA polling to indicate the end of a programming cycle. While the device is busy, any attempted read of the last byte written will return the data byte with the MSB complemented. Once the programming cycle has completed, the true value will be accessible ...
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... Sampling of pin P3.1 (RDY/BSY) is optional. During Parallel Programming, P3.1 will be pulled low while the device is busy. Note that it does not require an external passive pull- Figure 23-4 shows a generic parallel read command sequence. Command AAh OPCODE ADDRH AAh OPCODE ADDRH AT89LP2052/LP4052 2.7 to 5.5V VCC P1 DATA RST V PP Figure 23-3 shows a generic parallel write com- ADDRL ...
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... Bring RST/V 3. Bring XTAL and P3.2 to “L”. 4. Bring RST to “L” and wait 10 µs. 5. Power off V Figure 23-6. Parallel Mode Power-down Operation Note: AT89LP2052/LP4052 60 has settled, wait 10 µs and bring RST to “H” 12V to enable the parallel programming modes. PP has settled, wait an additional 10 µs before programming. ...
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... Drive P1 to 8Ah and pulse XTAL1 high. 4. Bring CS high. 5. Wait 4 ms, monitor P3.1, or poll data/status. Figure 23-8. Chip Erase Sequence RDY/BSY Note: 3547H–MICRO–5/ AAh ACh CS XTAL1 P1 AAh 8Ah The waveforms on this page are not to scale. AT89LP2052/LP4052 . In serial programming a session PP 53h 61 ...
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... Bytes should not be loaded more than once. 7. Bring CS high. Figure 23-9. Load Page Buffer Sequence CS XTAL1 P1 Note: AT89LP2052/LP4052 62 AAh 51h 00h The waveform on this page is not to scale. 000bbbbb DIN 0 ...
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... Note: 3547H–MICRO–5/ not possible to skip bytes while loading data during write. To load non-contiguous bytes in a page, use the Load Page Buffer command AAh 50h 0000aaaa aaabbbbb The waveform on this page is not to scale. AT89LP2052/LP4052 DIN 0 DIN 1 DIN n 63 ...
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... Read data from P1 read additional data bytes in the page, pulse XTAL1 high to increment to the next address. 10. Drive CS high. Figure 23-11. Read Code Page Sequence CS XTAL1 P1 Note: AT89LP2052/LP4052 64 AAh 30h 0000aaaa aaabbbbb The waveform on this page is not to scale. DOUT 0 DOUT 1 DOUTn 3547H–MICRO–5/07 ...
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... RDY/BSY Note: 3547H–MICRO–5/ not possible to skip bytes while loading data during write. To load non-contiguous bytes in a page, use the Load Page Buffer command. AAh 52h 00h The waveform on this page is not to scale. AT89LP2052/LP4052 000bbbbb DIN 0 DIN 1 DIN n 65 ...
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... Read data from P1 read additional data bytes in the page, pulse XTAL1 high to increment to the next address. 10. Drive CS high. Figure 23-13. Read User Signature Page Sequence CS XTAL1 P1 Note: AT89LP2052/LP4052 66 AAh 32h 00h The waveform on this page is not to scale. 000bbbbb DOUT 0 DOUT 1 DOUTn ...
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... To read additional data bytes in the page, pulse XTAL1 high to increment to the next address. 10. Drive CS high. Figure 23-14. Read Atmel Signature Page Sequence XTAL1 Note: 3547H–MICRO–5/ AAh 38h The waveform on this page is not to scale. AT89LP2052/LP4052 00h 000bbbbb DOUT 0 DOUT 1 DOUTn 67 ...
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... Drive P1 to 0x64 and pulse XTAL1 high. 4. Drive P1 to 0x00 and pulse XTAL1 high. 5. Drive P1 to 0x00 and bring XTAL1 high. 6. Tri-state P1. 7. Bring XTAL1 low. 8. Read data from P1. 9. Drive CS high. Figure 23-16. Read Lock Bits Sequence XTAL1 Note: AT89LP2052/LP4052 AAh E4h 00h CS P1 AAh 64h The waveforms on this page are not to scale ...
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... Tri-state P1. 7. Bring XTAL1 low. 8. Read data from P1. 9. Drive CS high. Figure 23-18. Read User Fuses Sequence XTAL1 Note: 3547H–MICRO–5/ AAh E1h 00h CS P1 AAh 61h The waveforms on this page are not to scale. AT89LP2052/LP4052 00h 1111FFFF 00h 00h 1111FFFF 69 ...
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... Drive P1 to 0x00 and pulse XTAL1 high. 5. Drive P1 to 0x00 and bring XTAL1 high. 6. Tri-state P1. 7. Bring XTAL1 low. 8. Read data from P1. 9. Drive CS high. Figure 23-19. Read Status Sequence XTAL1 Note: AT89LP2052/LP4052 AAh 60h The waveform on this page is not to scale. 00h 00h 1111SSSS 3547H– ...
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... Figure 23-20. Flash Programming and Verification Waveforms in Parallel Mode 3547H–MICRO–5/07 AT89LP2052/LP4052 71 ...
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... PWRDN 23.5 In-System Programming (ISP) The AT89LP2052/LP4052 offers a serial programming interface which may be used in place of the parallel programming interface or to program the device while in system. In this document serial programming and In-System Programming (ISP) refer to the same interface. ISP supports the same command set as parallel programming. However, during ISP command bytes are entered serially over the Serial Peripheral Interface (SPI) pins ...
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... Wait at least 2 ms for internal Power-on Reset to time out. Figure 23-22. Serial Programming Power-up Sequence 3547H–MICRO–5/07 AT89LP2052/LP4052 Serial Clock P1.7/SCK Serial Out P1.6/MISO Se rial In P1.5/MOSI CS P1.4/SS GND SCK frequency should be less than 5 MHz RST SS SCK MISO MOSI AT89LP2052/LP4052 2.7 to 5.5V VCC RST V IH HIGH Z HIGH Z 73 ...
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... Note: 23.5.3 ISP Start Sequence Execute this sequence to enter ISP when the device is already operational. 1. Bring SS (P1.4) to “H”. 2. Tri-state MISO (P1.6). 3. Bring RST to “H”. 4. Bring SCK (P1.7) to “L”. Figure 23-24. In-System Programming (ISP) Start Sequence AT89LP2052/LP4052 RST SS SCK MISO MOSI The waveforms on this page are not to scale. ...
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... MOSI is sampled at rising edge of SCK. Figure 23-26. ISP Byte Sequence 3547H–MICRO–5/ XTAL1 RST SS SCK MISO MOSI The waveforms on this page are not to scale. Figure SCK MOSI 7 6 MISO 7 6 Data Sampled AT89LP2052/LP4052 HIGH Z HIGH Z 23-26 ...
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... Output Enable Time SOE t Output Disable Time SOX t SS Enable Lead Time SSE t SS Disable Lag Time SSD t Wire Cycle Time WRC t Erase Cycle Time ERS AT89LP2052/LP4052 Opcode Address High X X Min 200 100 50 10 ...
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... SCK SSE t t SHSL SLSH SOV SOH SOE Note: AT89LP2052/LP4052 t t SSD SF t SOX t t SIS SIH Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional ...
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... Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Port in Quasi-Bidirectional Mode 3. Port in Push-Pull Output Mode 4. Minimum V for Power-down is 2V. CC AT89LP2052/LP4052 78 Condition (Except RST) (RST) (Except RST) (RST 2.7V ± ...
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... Serial Output Hold Time SOH t Serial Output Valid Time SOV t Output Enable Time SOE t Output Disable Time SOX t Slave Enable Lead Time SSE t Slave Disable Lag Time SSD 3547H–MICRO–5/07 AT89LP2052/LP4052 Min Max 41.6 4t CLCL SCK SCK ...
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... SCK (CPOL = 1) MISO MOSI Figure 24-2. SPI Slave Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL= 1) MISO MOSI Figure 24-3. SPI Master Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI AT89LP2052/LP4052 SCK t t SHSL SLSH t t SLSH SHSL t t SOH SOV t t ...
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... Figure 24-5. External Clock Drive Waveform Table 24-3. External Clock Drive Parameters Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL 3547H–MICRO–5/07 AT89LP2052/LP4052 V = 2.4V to 5.5V CC Min Max Units MHz ...
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... V IH (1) 24.6.2 Float Waveforms Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded V AT89LP2052/LP4052 82 (1) = 2.4V to 5.5V and Load Capacitance = 80 pF ...
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... V CC RST P1, P3 XTAL2 (NC) CLOCK SIGNAL XTAL1 GND Tests in Active and Idle Modes CHCL CHCX V RST CC P1, P3 (NC) XTAL2 XTAL1 GND AT89LP2052/LP4052 CLCH CHCL t CHCX t CLCH t CLCL = ...
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... Wide, Plastic Gull Wing Small Outline (SOIC) 20X 20-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) AT89LP2052/LP4052 84 Ordering Code Package AT89LP2052-20PI 20P3 AT89LP2052-20SI 20S2 AT89LP2052-20XI AT89LP4052-20PI 20P3 AT89LP4052-20SI 20S2 AT89LP4052-20XI Ordering Code Package AT89LP2052-20PU 20P3 AT89LP2052-20SU ...
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... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 3547H–MICRO–5/07 D PIN TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) AT89LP2052/LP4052 E1 A1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM A – – A1 0.381 – D 24.892 – ...
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... SOIC AT89LP2052/LP4052 86 3547H–MICRO–5/07 ...
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... PIN 1 4.50 (0.177) 4.30 (0.169) 6.60 (.260) 6.40 (.252) 0.15 (0.006) 0.30 (0.012) 0.05 (0.002) 0.19 (0.007) 0.75 (0.030) 0.45 (0.018) TITLE 20X, (Formerly 20T), 20-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) AT89LP2052/LP4052 INDEX MARK 6.50 (0.256) 6.25 (0.246) 1.20 (0.047) MAX SEATING PLANE 0.20 (0.008) 0.09 (0.004) DRAWING NO. 10/23/03 REV. 20X C 87 ...
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... Revision F – June 2006 • Revision G – April 2007 • • Revision H – May 2007 • AT89LP2052/LP4052 88 Initial Release Last paragraph in Section 13.2 on page 14 In Table 16-3 on page 25, changed the SFR address for TCONB from 88H to 91H. Changed the Maximum Bit Frequency from f/2 to f/4 in the “ ...
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... Oscillator Characteristics ..................................................................... 11 3547H–MICRO–5/07 2.120-lead PDIP/SOIC/TSSOP ......................................................................................2 5.1Program Memory .......................................................................................................4 5.2Data Memory .............................................................................................................5 7.1System Clock ............................................................................................................7 7.2Instruction Execution with Single-cycle Fetch ...........................................................7 7.3Interrupt Handling ......................................................................................................7 7.4Timer/Counters ..........................................................................................................7 7.5Serial Port ..................................................................................................................7 7.6Watchdog Timer ........................................................................................................7 7.7I/O Ports ....................................................................................................................8 7.8Reset .........................................................................................................................8 9.1Branching Instructions .............................................................................................10 9.2MOVX-related Instructions, Data Memory ...............................................................10 10.1Crystal Oscillator ...................................................................................................10 10.2External Clock Source ...........................................................................................10 10.3System Clock Out ..................................................................................................10 AT89LP2052/LP4052 i ...
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... Table of Contents (Continued) 12. Reset ....................................................................................................... 13 13. Power Saving Modes ............................................................................. 13 14. Interrupts ................................................................................................ 15 15. I/O Ports .................................................................................................. 19 16. Enhanced Timer/Counters .................................................................... 23 17. External Interrupts ................................................................................. 29 AT89LP2052/LP4052 ii 12.1Power-on Reset .....................................................................................................13 12.2Brown-out Reset ....................................................................................................13 12.3External Reset .......................................................................................................13 12.4Watchdog Reset ....................................................................................................13 13.1Idle Mode ...............................................................................................................14 13.2Power-down Mode ................................................................................................14 14.1Interrupt Response Time .......................................................................................16 15.1Quasi-bidirectional Output .....................................................................................19 15.2Input-only Mode .....................................................................................................20 15.3Open-drain Output .................................................................................................21 15.4Push-pull Output ....................................................................................................21 15 ...
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... Pin Configuration ............................................................................................47 20.1Comparator Interrupt with Debouncing .................................................................48 23.1Programming Command Summary .......................................................................57 23.2Status Register ......................................................................................................58 23.3DATA Polling .........................................................................................................58 23.4Parallel Programming ............................................................................................58 23.5In-System Programming (ISP) ...............................................................................72 24.1Absolute Maximum Ratings* .................................................................................77 24.2DC Characteristics ................................................................................................78 24.3Serial Peripheral Interface Timing ........................................................................79 24.4External Clock Drive ..............................................................................................81 24.5Serial Port Timing: Shift Register Mode ................................................................82 24.6Test Conditions .....................................................................................................82 AT89LP2052/LP4052 iii ...
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... Table of Contents (Continued) 25. Ordering Information ............................................................................. 84 26. Packaging Information .......................................................................... 85 27. Revision History ..................................................................................... 88 AT89LP2052/LP4052 iv 25.1Standard Package .................................................................................................84 25.2Green Package Option (Pb/Halide-free) ...............................................................84 26.120P3 – PDIP ..........................................................................................................85 26.220S2 – SOIC ........................................................................................................86 26.320X – TSSOP ........................................................................................................87 3547H–MICRO–5/07 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Operations Memory ...