sab-c167cs-l40m Infineon Technologies Corporation, sab-c167cs-l40m Datasheet
sab-c167cs-l40m
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Edition 2001-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms ...
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C167CS Revision History: Previous Version: Page Subjects (major changes from V2.1, 2000-12 to V2.2, 2001-08) 4 Figure 2 corrected (pins 98, 99) 25, 27 Figure 5 and 50ff Output voltage/current specification improved 52f Limit values for oscillator 54 Figure 10 ...
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Single-Chip Microcontroller C166 Family C167CS-4R, C167CS-L • High Performance 16-bit CPU with 4-Stage Pipeline – 80/60/50 ns Instruction Cycle Time at 25/33/40 MHz CPU Clock – 400/303/250 ns Multiplication (16 × 16 bit), 800/606/500 ns Division (32-/16-bit) – Enhanced ...
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... Table 1 C167CS Derivative Synopsis 1) Derivative SAK-C167CS-LM SAB-C167CS-LM SAK-C167CS-L33M SAB-C167CS-L33M SAK-C167CS-L40M SAB-C167CS-L40M SAK-C167CS-4RM SAB-C167CS-4RM SAK-C167CS-4R33M SAB-C167CS-4R33M SAK-C167CS-4R40M SAB-C167CS-4R40M 1) This Data Sheet is valid for devices starting with and including design step BA. For simplicity all versions are referred to by the term C167CS throughout this document. ...
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Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • the derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the ...
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Pin Configuration (top view) P6.0/CS0 1 2 P6.1/CS1 P6.2/CS2 3 P6.3/CS3 4 P6.4/CS4 5 P6.5/HOLD 6 P6.6/HLDA 7 P6.7/BREQ 8 *P8.0/CC16IO 9 *P8.1/CC17IO 10 *P8.2/CC18IO 11 *P8.3/CC19IO 12 P8.4/CC20IO 13 P8.5/CC21IO 14 P8.6/CC22IO 15 P8.7/CC23IO ...
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Table 2 Pin Definitions and Functions Symbol Pin Input Num. Outp P6.6 7 I/O P6 P8.0 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P7.4 23 I/O P7.5 24 I/O P7.6 25 I/O P7 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P2.0 47 I/O P2.1 48 I/O P2.2 49 I/O P2.3 50 I/O P2.4 51 I/O P2.5 52 I/O P2.6 53 I/O P2.7 54 I/O P2.8 57 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P3.8 75 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P4.7 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. ALE PORT0 IO P0L.0-7 100- 107 P0H.0-7 108, 111- 117 Data Sheet Function Address Latch Enable Output. Can be used for latching the ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. PORT1 IO P1L.0-7 118- 125 P1H.0-7 128- 135 P1L.0 118 I P1L.1 119 I P1L.2 120 I P1L.3 121 I P1L.4 122 I P1L.5 123 I P1L.6 124 ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. RSTIN 140 I/O RST 141 O OUT NMI 142 – AREF V 38 – AGND Data Sheet Function Reset Input with Schmitt-Trigger characteristics. A low ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. V 17, 46, – DD 56, 72, 82, 93, 109, 126, 136, 144 V 18, 45, – SS 55, 71, 83, 94, 110, 127, 139, 143 1) The ...
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... Register XPERCON selects the required modules which are then enabled by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules that are disabled consume neither address space nor port pins. Note: The default value of register XPERCON after reset selects 2 KByte XRAM and module CAN1, so the default XBUS resources are compatible with the C167CR ...
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... KByte, respectively, are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed. In order to meet the needs of designs where more memory is required than is provided on chip MBytes of external RAM and/or ROM can be connected to the microcontroller ...
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External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...
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... Port 4, the CAN lines override the segment address lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS lines can be used to increase the total amount of addressable external memory. Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs ...
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The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...
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Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C167CS is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...
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Table 3 C167CS Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM ...
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Table 3 C167CS Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 ...
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The C167CS also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse ...
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Table 5 Compare Modes (CAPCOM) Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible. Mode 1 Pin toggles on each compare match; several compare events per timer period are possible. Mode 2 Interrupt-only ...
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CPU TxIN GPT2 Timer T6 Over/Underflow CCxIO 16 Capture Inputs 16 Compare Outputs CCxIO CPU GPT2 Timer T6 Over/Underflow ...
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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD … 10 Figure 6 Block Diagram of GPT1 With its maximum resolution of ...
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This allows the C167CS to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN ...
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Real Time Clock The Real Time Clock (RTC) module of the C167CS consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). ...
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... In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via registers P5DIDIS (Port 5 Digital Input Disable) and P1DIDIS (PORT1 Digital Input Disable). Data Sheet 30 ...
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Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with ...
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... The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows ...
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... Parallel Ports The C167CS provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs ...
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... Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset. The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON. In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also no interrupt request will be generated in case of a missing oscillator clock ...
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... External circuitry can be controlled via the programmable frequency output FOUT. • Peripheral Management permits temporary disabling of peripheral modules (control via register SYSCON3). Each peripheral can separately be disabled/enabled. A group control option disables a major part of the peripheral set by setting one single bit. The on-chip RTC supports intermittent operation of the C167CS by generating cyclic wakeup signals ...
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... BAND, BOR, AND/OR/XOR direct bit with direct bit BXOR BCMP Compare direct bit to direct bit BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 ...
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... Software Reset IDLE Enter Idle Mode PWRDN Enter Power Down Mode (supposes NMI-pin being low) SRVWDT Service Watchdog Timer DISWDT Disable Watchdog Timer EINIT Signify End-of-Initialization on RSTOUT-pin ATOMIC Begin ATOMIC sequence EXTR Begin EXTended Register sequence EXTP(R) Begin EXTended Page (and Register) sequence ...
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... Table 7 lists all SFRs which are implemented in the C167CS in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “ ...
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Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address C1UAR EFn2 X --- H C1UGML EF08 X --- H C1UMLM EF0C X --- H C2BTR EE04 X --- H C2CSR EE00 X --- H C2GMS EE06 X --- ...
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Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address CC17 FE62 H CC17IC b F162 CC18 FE64 H CC18IC b F164 CC19 FE66 H CC19IC b F166 CC1IC b ...
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Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address CC30 FE7C H CC30IC b F18C CC31 FE7E H CC31IC b F194 CC3IC b FF7E H CC4 FE88 H CC4IC b FF80 H ...
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Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address DP1L b F104 DP1H b F106 DP2 b FFC2 H DP3 b FFC6 H DP4 b FFCA H DP6 b FFCE H DP7 ...
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... Port 1 Low Reg. (Lower half of PORT1 Port 2 Register H E2 Port 3 Register H E4 Port 4 Register (8 bits Port 5 Register (read only Port 5 Digital Input Disable Register H E6 Port 6 Register (8 bits Port 7 Register (8 bits Port 8 Register (8 bits PEC Channel 0 Control Register H 61 ...
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Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address POCON4 F08C POCON6 F08E POCON7 F090 POCON8 F092 PP0 F038 PP1 F03A E 1D ...
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Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address S0RBUF FEB2 H S0RIC b FF6E H S0TBIC b F19C S0TBUF FEB0 H S0TIC b FF6C H SP FE12 H SSCBR F0B4 SSCCON ...
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Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address T14 F0D2 T14REL F0D0 FE40 H T2CON b FF40 H T2IC b FF60 H T3 FE42 H T3CON b FF42 H T3IC ...
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Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address XP3IC b F19E XPERCON F024 ZEROS b FF1C H 1) The system configuration is selected during reset. 2) The reset value depends on ...
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Absolute Maximum Ratings Table 8 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature V Voltage on pins with DD V respect to ground ( ) SS Voltage on any pin with V respect to ground ( ) SS Input ...
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... < C167CS-4R C167CS-L Unit Notes V Active mode MHz CPUmax V PowerDown mode V Reference voltage 2)3) mA Per pin Pin drivers in fast edge mode ° C SAB-C167CS … ° C SAF-C167CS … ° C SAK-C167CS … - 0.5 V). The absolute sum of input overload V2.2, 2001-08 4) ...
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Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167CS and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ...
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DC Characteristics (cont’d) (Operating Conditions apply) Parameter Input leakage current (all other) 6) RSTIN inactive current 6) RSTIN active current READY/RD/WR inact. current READY/RD/WR active current 9) ALE inactive current 9) ALE active current 9) Port 6 inactive current 9) ...
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... PLL off, SDD factor = 32 Sleep and Power-down mode supply current with RTC running Sleep and Power-down mode supply current with RTC disabled 1) The supply current is a function of the operating frequency. This dependency is illustrated in These parameters are tested at at ...
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A] I 3000 2000 1000 10 Figure 9 Idle and Power Down Supply Current as a Function of Oscillator Frequency Data Sheet C167CS-4R C167CS-L I IDOmax I IDOtyp I PDRmax I PDOmax 40 f [MHz] ...
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I [mA] 140 120 100 Figure 10 Supply/Idle Current as a Function of Operating Frequency Data Sheet C167CS-4R C167CS-L I DD5max I DD5typ I IDX5max I IDX5typ 40 f [MHz] CPU V2.2, ...
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AC Characteristics Definition of Internal Timing The internal operation of the C167CS is controlled by the internal CPU clock edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external ...
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P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 11 associates the combinations of these three bits with the respective clock generation mode. Table 11 C167CS Clock Generation Modes CLKCFG CPU ...
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Due to this adaptation to the input clock the frequency locked to . The slight variation causes a jitter of OSC duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs ...
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... Direct Drive When direct drive is configured (CLKCFG = 011 disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. f The frequency of directly follows the frequency of CPU f (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock ...
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AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Table 12 External Clock Drive Characteristics Parameter Symbol t Oscillator period SR 25 OSC 2) t High time Low time Rise ...
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A/D Converter Characteristics (Operating Conditions apply) Table 13 A/D Converter Characteristics Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Calibration time after reset Total unadjusted error Internal resistance of reference voltage source ...
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As the default basic clock after reset is a valid factor as early as possible. A timeframe of approx. 6000 CPU clock cycles is sufficient to ensure a proper reset calibration. This corresponds to minimum 300 instructions (worst case: ...
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Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at Figure 14 Input Output Waveforms V + 0.1 V ...
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AC Characteristics Table 15 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to For a ...
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Table 17 External Bus Cycle Timing (Operating Conditions apply) Parameter Output delay from CLKOUT falling edge Valid for: address (MUX on PORT0), write data out Output delay from CLKOUT edge Valid for: latched CS, ALE (normal) Output delay from CLKOUT ...
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The bandwidth of a parameter (minimum and maximum value) covers the whole operating range (temperature, voltage) as well as process variations. Within a given device, however, this bandwidth is smaller than the specified range. This is also due to interdependencies ...
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CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A0, BHE WRL, WRH, WR, WrCS D15-D0 Note: Write data is deactivated 1 TCL earlier if early write is enabled (same timing). Figure 17 Demultiplexed Bus, Write ...
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CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A0, BHE RD, RdCS D15-D0 Figure 18 Demultiplexed Bus, Read Access Data Sheet Normal ALE Cycle Extended ALE Cycle ...
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CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A16, BHE WRL, WRH, WR, WrCS AD15-AD0 (Normal ALE AD15-AD0 (Extended ALE) Note: Write data is deactivated 2 TCL earlier if early write ...
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CLKOUT Normal ALE tc 19 Extended ALE tc 19 CSxE, CSxL tc 16 A23-A16, BHE RD, RdCS AD15-AD0 (Normal ALE AD15-AD0 (Extended ALE) Figure 20 Multiplexed Bus, Read Access Data Sheet Normal ALE Cycle tc 11 ...
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... READY sampled LOW at this sampling point terminates the currently running bus cycle the next following bus cycle is READY controlled, an active READY signal must be disabled before the first valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current cycle, and on the MCTC waitstates and the ALE mode of the next following cycle ...
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Running Cycle CLKOUT D15-D0 D15-D0 Command (RD, WR) Synchronous READY tc 25 Asynchronous 4) 3) READY Figure 21 READY Timing Data Sheet ...
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External Bus Arbitration Table 20 Bus Arbitration Timing (Operating Conditions apply) Parameter HOLD input setup time to CLKOUT falling edge CLKOUT to BREQ delay CLKOUT to HLDA delay 1) CSx release CSx drive 1) Other signals release 1) Other signals ...
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CLKOUT tc 28 HOLD HLDA BREQ CS Other Signals Figure 22 External Bus Arbitration, Releasing the Bus Notes 1) The C167CS will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ ...
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CLKOUT HOLD HLDA BREQ CS Other Signals Figure 23 External Bus Arbitration, (Regaining the Bus) Notes 4) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by ...
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External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C167CS can be accessed (during hold states external master like an asynchronous SRAM. Table 21 XRAM Access Timing (Operating Conditions apply) Parameter Address setup time ...
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Package Outlines P-MQFP-144-6 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 76 C167CS-4R C167CS-L Dimensions in mm V2.2, 2001-08 ...
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Infineon goes for Business Excellence “Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all ...