sta013b STMicroelectronics, sta013b Datasheet

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... D/A converter, by the PCM Out- put Interface. This interface is software program- mable to adapt the STA013 digital output to the most common DACs architectures used on the market. The functional STA013 chip partitioning is de- scribed in Fig.1. STA013 SO28 TQFP44 LFBGA64 STA013T$ (TQFP44) STA013B$ (LFBGA 8x8) 1/38 ...

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... STA013 - STA013B - STA013T Figure 1. Block Diagram: MPEG 2.5 Layer III Decoder Hardware Partitioning. RESET 26 5 SDI SERIAL 6 SCKR BUFFER INPUT INTERFACE 7 BIT_EN 8 28 SRC_INT OUT_CLK/DATA_REQ THERMAL DATA Symbol R Thermal resistance Junction to Ambient th j-amb ABSOLUTE MAXIMUM RATINGS Symbol V Power Supply DD V Voltage on Input pins ...

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... D99AU1019 SDI B2 = SCKR D4 = BIT_EN D1 = SRC_INT E2 = SDO F2 = SCKT H1 = LRCKT H3 = OCLK F3 = VSS_2 E4 = VDD_2 G4 = VSS_3 G5 = VDD_3 F5 = PVDD G6 = PVSS D99AU1085 LFBGA64 STA013 - STA013B - STA013T G7 = FILT G8 = XTO F7 = XTI E7 = VSS4 C8 = VDD4 D7 = TESTEN A7 = SCANEN B6 = RESET A5 = VSS5 C5 = OUT_CLK/DATA_REQ B5 = VDD1 B4 = VSS1 A4 = SDA B3 = SCL 3/38 ...

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... STA013 - STA013B - STA013T PIN DESCRIPTION SO28 TQFP44 LFBGA64 Pin Name VDD_1 VSS_1 BIT_EN SRC_INT LRCKT VSS_2 VDD_2 VSS_3 VDD_3 ...

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... Test Condition Min. 0.8 Xma ol 0.85*V Test Condition Min 0V; pin numbers and 26 Test Condition Min. Sampling_freq ≤24 kHz Sampling_freq ≤32 kHz Sampling_freq ≤48 kHz STA013 - STA013B - STA013T Value 2.4 to 3.6V Typ. Max. Unit Note µA -10 10 µA - Typ. Max. Unit Note 0.2*V V ...

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... STA013 - STA013B - STA013T Figure 3. Test Circuit OUT_CLK/DATA_REQ V DD 100nF 100nF 100nF 100nF 4.7µF 4.7µ Figure 4. Test Load Circuit OUTPUT FUNCTIONAL DESCRIPTION 2.1 - Clock Signal The STA013 input clock is derivated from an ex- ...

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... N user. The STA013 PLL can drive directly most of the commercial DACs families, providing an over sampling clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers. STA013 - STA013B - STA013T SDO SCKT DAC LRCKT OCLK IGNORED ...

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... STA013 - STA013B - STA013T Figure 7. PLL and Clocks Generation System XTI N FRAC Update FRAC 2.4 - PCM Output Interface The decoded audio data are output in serial PCM format. The interface consists of the following sig- nals: SDO PCM Serial Data Output SCKT PCM Serial Clock Output ...

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... Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. STA013 - STA013B - STA013T MUTE Clock State PCM Output 0 Not Running ...

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... STA013 - STA013B - STA013T 3.1.2 - Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition termi- nates communications between STA013 and the bus master. 3.1.3 - Acknowledge bit An acknowledge bit is used to indicate a success- ful data transfer ...

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... SYNCSTATUS $41 65 ANCCOUNT_L $42 66 ANCCOUNT_H STA013 - STA013B - STA013T terminates the transfer with a STOP condition. The output data stream is from consecutive byte addresses, with the internal byte address counter automatically incremented after one byte output REGISTERS The following table gives a description of the MPEG Source Decoder (STA013) register list ...

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... STA013 - STA013B - STA013T REGISTERS (continued) HEX_COD DEC_COD $43 67 HEAD_H[23:16] $44 68 HEAD_M[15:8] $45 69 HEAD_L[7:0] $46 70 DLA $47 71 DLB $48 72 DRA $49 73 DRB $50 80 MFSDF_441 $51 81 PLLFRAC_441_L $52 82 PLLFRAC_441_H $54 84 PCM DIVIDER $55 85 PCMCONF $56 86 PCMCROSS $59 89 ANC_DATA_1 [7:0] $5A 90 ANC_DATA_2 [15:8] $5B 91 ANC_DATA_3 [23:16] ...

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... STA013 PLL by DSP embedded software and N registers are R/W type but they are completely controlled, on STA013, by DSP soft- ware. REQ_POL Address: 0x0C Type: R/W Software Reset: 0x01 Hardware Reset: 0x00 STA013 - STA013B - STA013T LSB OCLK SYS2O PPLD XTI2DS XTI2O ...

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... STA013 - STA013B - STA013T Hardware Reset: 0x01 The REQ_POL registers is used to program the polarity of the DATA_REQ line. MSB Default polarity (the source sends data when the DATA_REQ line is high) MSB Inverted polarity (the source sends data when the ...

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... mode. The buffered Output Clock has the same fre- quency than the input clock (XTI SS1 STA013 - STA013B - STA013T C/Ancillary Data LSB b0 Description X buffered output clock X request signal LSB ...

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... STA013 - STA013B - STA013T ANCCOUNT_L Address: 0x41 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB AC7 AC6 AC5 AC4 AC3 AC2 ANCCOUNT_H Address: 0x42 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 ANCCOUNT_H MSB AC15 AC14 AC13 AC12 AC11 AC10 AC9 ...

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... This bit equals ’0’ if the bitstream is a copy, ’1’ original. 112 128 Emphasis 144 Indicates the type of de-emphasis that shall be used. 160 forbidden emphasis ’00’ none ’01’ 50/15 microseconds ’10’ reserved ’11’ CCITT J,17 MPEG2.5 11. reserved STA013 - STA013B - STA013T mode specified emphasis specified 17/38 ...

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... STA013 - STA013B - STA013T DLA Address: 0x46 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB DLA7 DLA6 DLA5 DLA4 DLA register is used to attenuate the level of audio output at the Left Channel using the butter- fly shown in Fig ...

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... The VCO output frequency, when decoding 44.1KHz bitstream, is divided by (MFSDF_441 +1) PLLFRAC_441_L Address: 0x51 Type: R/W LSB Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 PF7 PF6 STA013 - STA013B - STA013T LSB b0 Description OUTPUT ATTENUATION 0 NO ATTENUATION 1 -1dB 0 -2dB : : 0 -96dB the maximum attenuation LSB ...

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... STA013 - STA013B - STA013T PLLFRAC_441_H Address: 0x52 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB PF15 PF14 PF13 PF12 PF11 PF10 PF9 The registers are considered logically concate- nated and contain the fractional values for the PLL, for 44.1KHz reference frequency. ...

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... The PCM samples precision in STA013 can 18-20-24 bits. When STA013 operates in 16 (18-20-24) bits mode, the number of bits transmitted during a LRCLT period is 32 (64). STA013 - STA013B - STA013T Description PCM order the LS bit is transmitted First PCM order the MS bit is transmitted First The word is right padded ...

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... STA013 - STA013B - STA013T PCMCROSS Address: 0x56 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB The default configuration for this register is ’0x00’. ANCILLARY DATA BUFFER Address: 0x59 - 0x5D Type: RO ...

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... Address: 0x71 Type: RO FC1 FC0 MSB b7 b6 LSB SV7 SV6 After the STA013 boot, this register contains the version code of the embedded software. FC8 STA013 - STA013B - STA013T LSB LSB AB5 AB4 AB3 AB2 ...

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... STA013 - STA013B - STA013T RUN Address: 0x72 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB Setting this register to 1, STA013 leaves the idle state, starting the decoding process. The Microcontroller is allowed to set the RUN flag, once all the control registers have been in- itialized ...

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... LSB The allowed Attenuation/Enhancement range [-18dB, +18dB]. TE1 TE0 LSB STA013 - STA013B - STA013T ENHANCE/ATTENUATION 1.5dB step +18 +16.5 +15 +13 -13.5 -15 -16.5 -18 25/38 ...

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... STA013 - STA013B - STA013T BASS_ENHANCE Address: 0x7C Software Reset: 0x00 Hardware Reset: 0x00 MSB BE7 BE6 BE5 BE4 BE3 BE2 MSB ...

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... DESCALING SIDE INFORMATION DECODING pling frequencies. The time duration of the Layer III frames is shown in Tab STA013 - STA013B - STA013T audio, the full signal is ATTENUATION -1.5dB step 0dB -1.5dB -3dB -4.5dB -15dB -16.5dB -18dB INVERSE IMDCT FILTERBANK STEREOPHONIC AUDIO ...

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... STA013 - STA013B - STA013T The Ancillary Data extraction on STA013 can be described as follow: STA013 has a specific Ancillary Data buffer, mapped into the I2C registers: 0x59 ANC_DATA_1 0x5A ANC_DATA_2 0x5B ANC_DATA_3 0x5C ANC_DATA_4 0x5D ANC_DATA_5 Since the content of Ancillary Data into an MPEG Frame STA013 can extract is max. 56 bytes ...

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... OCLK) b) OCLK in input. OCLK (INPUT) SDO SCKT LRCLK Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns STA013 - STA013B - STA013T t sdo t sckt t lrclk D98AU969 Pad-timing versus load Load (pF 100 Cload_XXX is the load the XXX output ...

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... STA013 - STA013B - STA013T 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0 BIT_EN SCKR SDI 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1 BIT_EN SCKR IGNORED SDI tsdi_setup_min = 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns 5.4.3. SRC_INT This is an asynchronous input used in "broadcast’ mode. ...

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... PLL FRAC_L } set { MFS DF_441, MFSDF } set PLL CTRL set SCLK_POL set DATA_REQ_ENABLE set REQ_POL set RUN STA013 - STA013B - STA013T t reset_low_min PCM OUTPUT INTERFACE THE OVERALL CONFIGURATION SETTING STEPS ARE INCLUDED IN THE STA013 CONFIGURATION FILE AND CAN BE DOWNLOADED PLL IN ONE STEP. ...

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... STA013 - STA013B - STA013T Table 5: PLL Configuration Sequence For 10MHz Input Clock 256 Oversapling Clock REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL Table 6: PLL Configuration Sequence For 10MHz Input Clock 384 Oversapling Rathio REGISTER ...

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... REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL STA013 - STA013B - STA013T Table 11: PLL Configuration Sequence For 14.7456MHz Input Clock 384 Oversapling Rathio REGISTER VALUE ADDRESS 11 6 reserved 3 11 reserved 6 97 MFSDF ( MFSDF-441 3 101 ...

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... STA013 - STA013B - STA013T 5.6. STA013 CONFIGURATION FILE FORMAT The STA013 Configuration File is an ASCII format. An example of the file format is the following 128 15 ............ sequence of rows and each one can be interpreted The first part of the row is the I C address (register) and the second one is the I To download the STA013 configuration file into the device, a sequence of write operation to STA013 I interface must be performed ...

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... DIM. MIN. TYP. MAX. MIN. A 2.65 a1 0.1 0.3 0.004 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0.5 c1 45° (typ.) D 17.7 18.1 0.697 E 10 10.65 0.394 e 1.27 e3 16.51 F 7.4 7.6 0.291 L 0.4 1.27 0.016 8 ° (max.) S STA013 - STA013B - STA013T inch OUTLINE AND MECHANICAL DATA TYP. MAX. 0.104 0.012 0.019 0.013 0.020 0.713 0.419 0.050 0.65 0.299 0.050 SO28 35/38 ...

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... STA013 - STA013B - STA013T mm DIM. MIN. TYP. MAX. MIN. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.30 0.37 0.45 0.012 C 0.09 0.20 0.004 D 11.80 12.00 12.20 0.464 D1 9.80 10.00 10.20 0.386 D3 8.00 E 11.80 12.00 12.20 0.464 E1 9.80 10.00 10.20 0.386 E3 8.00 e 0.80 L 0.45 0.60 0.75 0.018 L1 1.00 k 0˚(min.), 3.5˚(typ.), 7˚(max 36/38 inch TYP. MAX. MECHANICAL DATA 0.063 0.006 0.055 0.057 0.015 0.018 ...

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... BALL 1 IDENTIFICATION φ b (64 PLACES) e STA013 - STA013B - STA013T inch MECHANICAL DATA TYP. MAX. 0.067 0.016 0.018 0.043 0.20 0.315 0.220 0.031 Body 1.7mm 0.315 0.220 0.047 0. LFBGA64M ...

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... STA013 - STA013B - STA013T Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...