sta015t-013tr STMicroelectronics, sta015t-013tr Datasheet
sta015t-013tr
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sta015t-013tr Summary of contents
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... S AND by the PCM Output Interface. This interface is software programmable to adapt the STA015 digital output to the most common DACs architectures used on the market. The func- tional STA015 chip partitioning is described in Fig.1a and Fig.1b. STA015 TQFP44 LFBGA64 STA015T$ (TQFP44) STA015B$ (LFBGA 8x8) 1/55 ...
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... STA015 STA015B STA015T Figure 1. 1a. Block Diagram for TQFP44 and LFBGA64 package. TQFP44 34 SDI SERIAL 36 SCKR INPUT INTERFACE 38 BIT_EN 27 BUFFER DATA-REQ 256 SCK_ADC ADC 26 LRCK_ADC INPUT INTERFACE 24 SDI_ADC 25 RESET 1b. BLOCK DIAGRAM for SO28 package SO28 5 SDI SERIAL 6 SCKR INPUT INTERFACE ...
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... E2 = SDO C8 = VDD_4 F2 = SCKT D7 = TESTEN H1 = LRCKT A7 = SDI_ADC H3 = OCLK B6 = RESET F3 = VSS_2 A5 = LRCK_ADC E4 = VDD_2 C5 = OUT_CLK/DATA_REQ G4 = VSS_3 B5 = VDD_1 G5 = VDD_3 B4 = VSS_1 F5 = PVDD A4 = SDA G6 = PVSS B3 = SCL LFBGA64 STA015 STA015B STA015T GPSO_SCKR LRCK_ADC RESET SDI_ADC TESTEN VDD_4 VSS_4 XTI XTO FILT PVSS PVDD VDD_3 VSS_3 33 GPSO_DATA 32 SCL 31 SDA ...
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... STA015 STA015B STA015T 1.0 OVERVIEW 1.1 MP3 decoder engine The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5 streams are supported. Besides audio data decoding the MP3 engine also performs ANCIL- LARY data extraction: these data can be retrieved via I to implement specific functions ...
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... O GPSO Request Signal GPSO_SCKR I GPSO Serial Clock GPSO_DATA O GPSO Serial Data STA015 STA015B STA015T Function PAD Description CMOS Input Pad Buffer CMOS 4mA Output Drive CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer CMOS Input Pad Buffer ...
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... STA015 STA015B STA015T ELECTRICAL CHARACTERISTICS: V specified DC OPERATING CONDITIONS Symbol V Power Supply Voltage DD T Operating Junction Temperature j GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input Current IL Without pull-up device I High Level Input Current IH Without pull-up device V Electrostatic Protection esd Notes: 1. The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin ...
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... High Level Input Voltage 100nF RESET Test Load V DD Output SDA V REF Other Outputs D98AU967 Test Condition STA015 STA015B STA015T SDA 3 SCL 4 SDO 9 SCKT 10 LRCKT 11 OCLK 12 SDI 5 SCKR 6 BIT_EN 7 SDI_ADC 25 SCR_INT 8 LRCK_ADC 27 XTI 21 XTO 20 10K ...
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... STA015 STA015B STA015T CMOS compatibility The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS pads. TTL compatibility The XTI pad low level is compatible with TTL while the high level is not compatible (for example TTL min high level = 2.0V while XTI min high level = 2.2V) 2.2 PLL & ...
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... MUTE to 1). MUTE to 1). PLAY link after device power-on. Please contact SOURCE STOPS TRANSMITTING DATA SOURCE SEND DATA TO STA015 2 C registers description. MUTE Clock State 0 Not Running 1 Running STA015 STA015B STA015T D00AU1144 PCM Output 0 0 9/55 ...
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... STA015 STA015B STA015T Init Mode "PLAY" and "MUTE" changes are ignored in this mode. The internal state of the decoder will be updated only when the decoder changes from the state "init" to the state "decode". The "init" phase ends when the first decoded samples are at the output stage of the device. ...
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... GPSO_SCKR input clock; the GPSO_REQ request signal polarity (usually connected to an MCU interrupt line) can be configured as well. Figure 9. PCM Output Formats Table 1. MPEG Sampling Rates (KHz) MPEG 1 48 44.1 32 STA015 STA015B STA015T MPEG 2 24 22.05 16 MPEG 2.5 12 11.025 8 ...
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... STA015 STA015B STA015T 3.4 ADC Inteface Beside the serial input interface based on SDI and SCKR lines a 3 wire flexible and user configurable input interface is also available, suitable to interface with most A/D converters. To configure this interface 4 spe- 2 cific I C registers are available (ADC_ENABLE, ADC_CONF, ADC_WLEN and ADC_WPOS). Refer to registers description for more details ...
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... I C DATA_REQ LRCKT SCKT SDI_ADC STA015 SO28 TQFP44 LFBGA64 DATA_REQ STA015 LRCK_ADC SO28 SCK_ADC TQFP44 SDI_ADC LFBGA64 STA015 STA015B STA015T GPSO_REQ GPSO GPSO_DATA GPSO_SCKR SDA SCL DATA_REQ D99AU1064 LRCKT SCKT DAC SDO OCLK D99AU1121A SDO DAC OCLK LRCKT SCKT ...
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... STA015 STA015B STA015T Figure 14. Input from BITSTREAM, Output from GPSO MCU Figure 15. Input from ADC, Output from GPSO GPSO_DATA GPSO_SCKR MCU GPSO_REQ LRCK_ADC SCK_ADC ADC MASTER 2 5 BUS SPECIFICATION 2 The STA015 supports the I C protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver ...
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... RW NO ACK DATA STOP ACK ACK SUB-ADDR DEV-ADDR START RW ACK ACK DATA DATA ACK ACK SUB-ADDR DEV-ADDR START RW STA015 STA015B STA015T ACK STOP ACK ACK DATA IN D98AU825B NO ACK DATA STOP NO ACK DATA STOP ACK ACK DATA DATA DATA D98AU826A STOP NO ACK ...
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... STA015 STA015B STA015T 5.4 READ OPERATION (see Fig. 17) 5.4.1 Current byte address read The STA015 has an internal byte address counter. Each time a byte is written or read, this counter is in- cremented. For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1 ...
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... AVERAGE_BITRATE SOFTVERSION RUN TREBLE_FREQUENCY_LOW TREBLE_FREQUENCY_HIGH BASS_FREQUENCY_LOW BASS_FREQUENCY_HIGH TREBLE_ENHANCE BASS_ENHANCE TONE_ATTEN ANC_DATA_1 to ANC_DATA_56 ISR ADPCM_CONFIG GPSO_ENABLE GPSO_CONF ADC_ENABLE ADC_CONF ADPCM_FRAME_SIZE ADPCM_INT_CFG GPIO_CONF ADC_ WLEN ADC_ WPOS ADPCM_SKIP_FRAME STA015 STA015B STA015T 0x00 R(8) 0x00 R/W (8) 0xFF R/W (8) 0x00 R/W (8) 0xFF R/W (8) 0x00 R/W (2) 0x00 R/W (1) 0x00 R/W (8) 0x00 R/W (8) 0x00 R/W (1) 0x00 R/W (8) 0x00 ...
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... STA015 STA015B STA015T 6.1 STA015 REGISTERS DESCRIPTION The STA015 device includes 128 I scribed. The undocumented registers are reserved. These registers must never be accessed (in Read or in Write mode). The Read-Only registers must never be written. The following table describes the meaning of the abbreviations used in the I ...
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... Default polarity (the source sends data when the DATA_REQ line is high) MSB Inverted polarity (the source sends data when the ATA_REQ line is low STA015 STA015B STA015T LSB LSB 19/55 ...
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... STA015 STA015B STA015T SCKL_POL Address: 0x0D (13) Type: R/W Software Reset: 0x04 Hardware Reset: 0x04 MSB don’t care SCKL_POL is used to select the working polarity of the Input Serial Clock (SCKR). (1) If SCKL_POL is set to 0x00, the data (SDI) are sent with the falling edge of SCKR and sampled on the rising edge ...
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... X = don’t care normal operation mute The MUTE command is handled according to the state of the decoder, as described in section 2.5. MUTE sets the clock running STA015 STA015B STA015T LSB LSB LSB b2 b1 ...
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... STA015 STA015B STA015T CMD_INTERRUPT Address: 0x16 (22) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB don’t care normal operation write into I C/Ancillary Data The INTERRUPT is used to give STA015 the command to write into the I ters: 0x7E ... 0xB5). Every time the Master has to extract the new buffer content it writes into this register, setting non-zero value ...
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... don’t care ENCODED DATA AC5 AC4 AC3 AC13 AC12 AC11 H20 H19 STA015 STA015B STA015T LSB LSB AC2 AC1 AC0 LSB AC10 AC9 AC8 LSB H18 H17 H16 ...
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... STA015 STA015B STA015T HEAD_M[15:8] MSB b7 b6 H15 H14 HEAD_L[7:0] MSB Address: 0x43, 0x44, 0x45 (67, 68, 69) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 Head[1:0] emphasis Head[2] original/copy Head[3] copyrightHead [5:4] mode extension Head[7:6] mode Head[8] private bit Head[9] padding bit Head[11:10] sampling frequency index ...
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... MPEG1 MPEG2 44.1 22. reserved reserved mode specified stereo joint stereo (intensity_stereo and/or ms_stereo) dual_channel single_channel (mono) STA015 STA015B STA015T free 112 128 144 160 forbidden MPEG2.5 11. reserved ...
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... STA015 STA015B STA015T Mode extension These bits are used in joint stereo mode. They indicates which type of joint stereo coding method is ap- plied. The frequency ranges, over which the intensity_stereo and ms_stereo modes are applied, are im- plicit in the algorithm. Copyright If this bit is equal to ’0’, there is no copyright on the bitstream, ’1’ means copyright protected. ...
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... DRA4 DRA3 DRA2 DRA1 STA015 STA015B STA015T LSB b0 Description DLB0 OUTPUT ATTENUATION 0 NO ATTENUATION 1 -1dB 0 -2dB : : : 0 -96dB LSB b0 Description DRA0 OUTPUT ATTENUATION 0 NO ATTENUATION 1 -1dB 0 -2dB : : 0 -96dB 27/55 ...
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... STA015 STA015B STA015T DRB Address: 0x49 (73) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF MSB DRB7 DRB6 DRB5 DRB register is used to re-direct the Right Channel on the Left mix both the Channels. Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel. ...
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... This bit signal ADPCM encoded data are ready to be retrieved. PLLFRAC_441_H Address: 0x52 (82) Type: R/W Software Reset: 0x00 PF5 PF4 PF3 STA015 STA015B STA015T LSB LSB PF2 PF1 PF0 LSB ADR 29/55 ...
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... STA015 STA015B STA015T Hardware Reset: 0x00 MSB b7 b6 PF15 PF14 The registers are considered logically concatenated and contain the fractional values for the PLL, for 44.1KHz reference frequency. (see also PLLFRAC_L and PLLFRAC_H registers) ADPCM_SAMPLE_FREQ Address: 0x53 (83) Type: R/W Software Reset: 0x00 ...
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... FOR SCL PREC (1) PREC ( STA015 STA015B STA015T LSB b0 Description PD0 1 16 bit mode 512 bit mode 384 bit mode 256 bit mode 512 bit mode 384 x Fs ...
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... STA015 STA015B STA015T PCMCONF is used to set the PCM Output Interface configuration: ORD: PCM order. If this bit is set to’1’, the LS Bit is transmitted first, otherwise MS Bit is transmiited first. DIF: PCM_DIFF used to select the position of the valid data into the transmitted word. This setting is significant only in 18/20/24 bit/word mode. set to ’ ...
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... Left channel is duplicated on both Output channels Right channel is duplicated on both Output channels Right and Left channels are toggled STA015 STA015B STA015T Description LSB LSB MODE 33/55 ...
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... STA015 STA015B STA015T the default OCLK frequency is 12.288 MHz. PLLFRAC_L ([7:0]) MSB b7 b6 PF7 PF6 PLLFRAC_H ([15:8]) MSB b7 b6 PF15 PF14 Address: 0x64 - 0x65 (100 - 101) Type: R/W Software Reset: 0x46 | 0x5B Hardware Reset: 0xNA | 0x5B The registers are considered logically concatenated and contain the fractional values for the PLL, used to select the internal configuration ...
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... The Microcontroller is allowed to set the RUN flag, once all the control registers have been initialized AB5 AB4 AB3 SV5 SV4 SV3 STA015 STA015B STA015T LSB AB2 AB1 AB0 LSB SV2 SV1 SV0 LSB ...
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... STA015 STA015B STA015T TREBLE_FREQUENCY_LOW Address: 0x77 (119) Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 TF7 TF6 TREBLE_FREQUENCY_HIGH Address: 0x78 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 TF15 TF14 The registers TREBLE_FREQUENCY-HIGH and TREBLE_FREQUENCY-LOW, logically concatenated bit wide register, are used to select the frequency, in Hz, where the selected frequency is +12dB respect to the stop band. By setting these registers, the following rule must be kept: Treble_Freq < ...
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... STA015 STA015B STA015T TE2 TE1 LSB ENHANCE/ATTENUATION b0 1.5dB step 0 +18 1 +16.5 0 +15 1 +13.5 ...
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... STA015 STA015B STA015T BASS_ENHANCE Address: 0x7C (1240 Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 BE7 BE6 Signed number (2 complement) This register is used to select the enhancement or attenuation STA015 has to perform on Bass Frequency range at the digital signal. A decrement (increment decimal unit corresponds to a step of attenuation (enhancement ...
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... Address: 0xB6 (182) Type: R/W Software Reset: 0x00 LSB 0x7E ANC_DATA_1 ....... ....... ....... ....... ....... ....... 0xB5 ANC_DATA_56 0xB6 ISR STA015 STA015B STA015T ATTENUATION 1.5dB step 0dB -1.5dB 3dB 4.5dB : : -15 -16.5 -18 39/55 ...
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... STA015 STA015B STA015T Hardware Reset: 0x00 MSB don’t care ancillary data 1 = Ancillary Data Available The ISR is used by the microcontroller to understand when a new ancillary data block is available. After all ancillary data has been retrieved this bit must be cleared. ...
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... If ADCEN bit is set data to be encoded comes from ADC interface, otherwise data comes from MP3 stream interface STA015 STA015B STA015T LSB GEN LSB GRP GSP LSB ...
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... STA015 STA015B STA015T ADC_CONF Address: 0xBC (188) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB Using this register the ADC input interface can be configured as follow: 2 AIIS: ADC I S mode 0 = sample word must be aligned with LRCK ( sample word not aligned with LRCK (I ADC: ADC Data Config ...
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... GOSP: GPIO Strobe Polarity in OUTPUT mode 0 = non inverted 1 = inverted AFS5 AFS4 AFS3 INTL4 INTL3 INTL2 STA015 STA015B STA015T LSB AFS2 AFS1 AFS0 LSB INTL1 INTL0 X LSB GOSP GISP ...
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... STA015 STA015B STA015T ADC_WLEN Address: 0xC0 (192) Type: R/W Software Reset: 0x0F Hardware Reset: 0x0F MSB select ADC word length AWL4 through AWL0 bits can be used. This 5 bit value must contain the size of the significant data bits minus one. ADC_WPOS ...
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... Pin numbers 14, 16, 18, 20, 35, 37, 39, 41 OUTPUT PIN Z D98AU904 INPUT CAPACITANCE IO PIN IO D98AU905 INPUT PIN Z D98AU906 INPUT PIN Z D98AU907 INPUT IO CAPACITANCE PIN IO D00AU1150 STA015 STA015B STA015T MAX LOAD Z 100pF OUTPUT MAX LOAD PIN 5pF IO 100pF CAPACITANCE A 3.5pF CAPACITANCE A 3.5pF OUTPUT MAX LOAD PIN 5pF IO 100pF 45/55 ...
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... STA015 STA015B STA015T 6.3 TIMING DIAGRAMS 6.3.1 Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC OCLK (OUTPUT) SDO SCKT LRCLK tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK) tlrckt = 3.5 + pad_timing (Cload_LRCCKT) - pad_timing (Cload_ OCLK) Pad-timing versus load Cload_XXX is the load the XXX output ...
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... VALID IGNORED t t sdi_setup sdi_hold t t _biten _biten t sckr_min_period t sckr_min_low t sckr_min_high IGNORED VALID t t sdi_setup sdi_hold t t _src_hi _src_low STA015 STA015B STA015T SCLK_POL=0 D98AU971A SCLK_POL=4 IGNORED D99AU1038 D98AU972 47/55 ...
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... STA015 STA015B STA015T 6.3.5 XTI,XTO and CLK_OUT timings XTI (INPUT) XTO t CLK_OUT t clk_out txto = 1.40 + pad_timing (Cload_XTO) ns tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns Note: In "multimedia" mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between the XTI input and this pad. 6.3.6 RESET The Reset min duration (t_reset_low_min) is 100ns RESET 6 ...
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... Input Clock 384 Oversapling Rathio REGISTER VALUE ADDRESS 110 101 160 82 152 100 186 81 161 5 STA015 STA015B STA015T NAME VALUE reserved 12 reserved 3 MFSDF (x) 15 MFSDF-441 16 PLLFRAC-H 187 PLLFRAC-441-H 103 PLLFRAC-L 58 PLLFRAC-441-L 119 PLLCTRL 161 NAME VALUE ...
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... STA015 STA015B STA015T Table 6. PLL Configuration Sequence For 14.31818MHz Input Clock 512 Oversapling Rathio REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL Table 7. PLL Configuration Sequence For 14.7456MHz Input Clock 256 Oversapling Rathio REGISTER ...
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... STA015 device address /* write data 2 /* generate I C stop condition /* update pointer to new file row /* repeat until End of File /* End routine 2 STA015 STA015B STA015T 2 C command. The first part of the row interface must be performed. C registers default values are loaded after an internal DSP */ */ */ ...
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... STA015 STA015B STA015T mm DIM. MIN. TYP. MAX. A 2.65 a1 0.1 0.3 b 0.35 0.49 b1 0.23 0.32 C 0.5 c1 45° (typ.) D 17.7 18 10.65 e 1.27 e3 16.51 F 7.4 7.6 L 0.4 1.27 8 ° (max.) S 52/55 inch MIN. TYP. MAX. 0.104 0.004 0.012 0.014 0.019 0.009 0.013 0.020 0.697 0.713 0.394 0.419 0.050 0.65 0.291 0.299 0.016 0.050 OUTLINE AND ...
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... MECHANICAL DATA 0.063 0.006 0.055 0.057 0.015 0.018 0.008 0.472 0.480 0.394 0.401 0.315 0.472 0.480 0.394 0.401 0.315 0.031 0.024 0.030 TQFP44 ( 1.4mm) 0.039 TQFP4410 STA015 STA015B STA015T OUTLINE AND 0.10mm .004 Seating Plane C K 0076922 D 53/55 ...
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... STA015 STA015B STA015T mm DIM. MIN. TYP. MAX. A 1.700 A1 0.350 0.400 0.450 A2 1.100 b 0.500 D 8.000 D1 5.600 e 0.800 E 8.000 E1 5.600 f 1.200 BALL 1 IDENTIFICATION φ b (64 PLACES) e 54/55 inch MIN. TYP. MAX. 0.067 0.014 0.016 0.018 0.043 ...
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