sta003t STMicroelectronics, sta003t Datasheet
sta003t
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sta003t Summary of contents
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... S mono, or dual channel digital output that can be sent directly to a D/A converter, by the PCM Out- put Interface. This interface is software program- mable to adapt the STA003T digital output to the most common DACs architectures used on the market. The functional STA003T chip partitioning is de- scribed in Fig.1. ...
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... BIT_EN 8 28 SRC_INT VDD_5/CLK_OUT Figure 2. PIN CONNECTION VDD_1 VSS_1 SCKR BIT_EN SRC_INT SDO SCKT LRCKT OCLK VSS_2 VDD_2 Fig. 2 describes the STA003T pinout in SO28 package THERMAL DATA Symbol R Thermal resistance Junction to Ambient th j-amb 2/32 SDA SCL CONTROL CHANNEL MPEG 2.5 CONFIG. ...
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... CMOS 4mA Output Drive CMOS 4mA Output Drive Specific Level Input Pad (see paragraph 2.1) CMOS Input Pad Buffer with pull up CMOS Input Pad Buffer CMOS Input Pad Buffer with pull up CMOS 4mA Output Drive Parameter STA003T PAD Description Value Unit -0 -0 +0.3 ...
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... STA003T 1. ELECTRICAL CHARACTERISTICS: V specified DC OPERATING CONDITIONS Symbol V Power Supply Voltage DD T Operating Junction Temperature j GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input Current IL Without pull-up device I High Level Input Current IH Without pull-up device V Electrostatic Protection esd Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin ...
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... SS Test Load Circuit I OL OUTPUT FUNCTIONAL DESCRIPTION 2.1 - Clock Signal The STA003T input clock is derivated from an ex- ternal source or from a 14.72 MHz crystal. Symbol Parameter V Low Level Input Voltage IL V High Level Input Voltage IH CMOS compatibility The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS pads ...
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... Sampling Frequency (LRCKT) in steps of few ppm to compensate dynamically the audio sam- pling rate offset between the receiver and the broadcasting station. The compensation is done by the STA003T core without requiring interaction with the application controller and the sampling rate compensation produces a jittering effect outside the audible range ...
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... Switching Circuit XTI2OCLK XTI2DSPCLK as external timer source, STA003T performs the compensation of the audio sampling rate. The sampling rate control is done by the STA003T core, by setting PLLFRAC internal reg- ister. The PLLFRAC value is updated, in steps of few ppms, by Update PLLFRAC signal. t LOW t INT 432 ms 18 for 48 & ...
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... Data can be output either with the most signifi- cant bit first (MS) or least significant bit first (LS), selected by writing into a flag of the PCMCONF register. Figure 8 gives a description of the STA003T PCM Output Formats. The sample rates set decoded by STA003T is de- scribed in Table 1. 16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles M ...
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... SCL line is low. 3.2 - DEVICE ADDRESSING To start communication between the master and the STA003T, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode ...
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... Sequential address read This mode can be initiated with either a current address read or a random address read. How- ever in this case the master does acknowledge the data byte output and the STA003T continues to output the next byte in sequence. To terminate the streams of bytes the master 2 ...
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... TREBLE_ENHANCE 0x7C 124 BASS_ENHANCE 0x7D 125 TONE_ATTEN Note: 1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information. 2) RESERVED: register used for production test only, or for future use. DESCRIPTION STA003T RESET R/W 0x00 W (8) 0x01 R/W(8) 0x00 R/W(8) 0x00 R/W(8) 0x00 ...
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... Type: R Software Reset: 0x00 Hardware Reset: 0x00 The M and N registers are used to configure the STA003T PLL by DSP embedded software. M and N registers are R/W type but they are completely controlled, on STA003T, by DSP soft- ware OCLK SYS2O PPLD XTI2DS XTI2O ...
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... ( don’t care normal operation reset When this register is written, a soft reset occours. The STA003T core command register and the in- terrupt register are cleared. The decoder goes in to idle mode. PLAY Address: 0x13 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 ...
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... X = don’t care normal operation write into I The INTERRUPT is used to give STA003T the command to write into the I2C/Ancillary Data Buffer (Registers: 0x59 ... 0x5D). Every time the Master has to extract the new buffer content (5 bytes) it writes into this register, setting ...
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... Head[20] ID_ex H18 H17 H16 The HEAD registers can be viewed as logically concatenated to store the MPEG Layer III Header content. The set of three registers is updated every time the synchronisation to the new MPEG frame is achieved . STA003T LSB H13 H12 H1‘1 H10 H9 ...
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... STA003T The meaning of the flags are shown in the follow- ing tables: MPEG IDs IDex Layer in Layer III these two flags must be set always to "01". Protection_bit It equals "1" redundancy has been added and "0" if redundancy has been added. ...
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... DLB2 DLB1 DLB0 Default value is 0x00, corresponding at the maxi- mum attenuation in the re-direction channel. STA003T Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB the maximum attenuation D97AU667 Description OUTPUT ATTENUATION NO ATTENUATION -1dB -2dB : -96dB 17/32 is ...
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... STA003T DRA Address: 0x48 Type: R/W Software Reset: 0X00 Hardware Reset: 0X00 MSB DRA7 DRA6 DRA5 DRA4 DRA register is used to attenuate the level of audio output at the Right Channel using the but- terfly shown in Fig. 11. When the register is set to ...
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... PCM Mode O_FAC = 512 ; PCMDIVIDER = 3 O_FAC = 256 ; PCMDIVIDER = 1 O_FAC = 384 ; PCMDIVIDER = 2 STA003T Description 16 bit mode 512 bit mode 384 bit mode 256 bit mode 512 bit mode 384 bit mode ...
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... LCKT period) ’10’: 20 bit (32 slots transmitted per LCKT period) ’11’: 24 bit (32 slots transmitted per LCKT period) The PCM samples precision in STA003T can 18-20-24 bits. When STA003T operates with a 16 (18-20-24) bits precision, the number of bits transmitted dur- ing a LRCKT period is 32 (64) ...
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... Right channel is duplicated on both Output channels Right and Left channels are toggled The value is changed by the internal STA003T Core, to set the clock frequencies, according to the incoming bitstream. This value can be even set by the user to select the PCM interface con- figuration. ...
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... The value is rounded with an accuracy of 1 Kbit/sec. SOFTVERSION Address: 0x71 LSB Type MSB FC2 FC1 FC0 b7 b6 SV7 SV6 LSB After the STA003T boot, this register contains the version code of the embedded software. FC8 LSB LSB ...
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... Setting this register to 1, STA003T leaves the idle state, starting the decoding process. The Microcontroller is allowed to set the RUN flag, once all the control registers have been in- itialized. TREBLE_FREQUENCY_LOW Address: 0x77 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 ...
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... Signed number (2 complement) This register is used to select the enhancement or attenuation STA003T has to perform on Treble Frequency range at the digital signal. A decrement (increment decimal unit corre- sponds to a step of attenuation (enhancement) of 1.5dB. LSB The allowed Attenuation/Enhancement range [-18dB, +18dB] ...
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... Signed number (2 complement) This register is used to select the enhancement or attenuation STA003T has to perform on Bass Frequency range at the digital signal. A decrement (increment decimal unit corre- sponds to a step of attenuation (enhancement) of 1.5dB. LSB The allowed Attenuation/Enhancement range [-18dB, +18dB] ...
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... STA003T TONE_ATTEN Address: 0x7D Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB TA7 TA6 TA5 TA4 TA3 MSB GENERAL INFORMATION 5 ...
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... The Ancillary Data extraction on STA003T can be described as follow: STA003T has a specific 5 bytes Ancillary Data buffer, mapped into the I2C registers: 0x59 ANC_DATA_1 0x5A ANC_DATA_2 0x5B ANC_DATA_3 0x5C ANC_DATA_4 0x5D ANC_DATA_5 Since the content of Ancillary Data into an MPEG 5.3. I/O CELL DESCRIPTION 1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 9, 10, 11, 20, 28 ...
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... STA003T 5.4. TIMING DIAGRAMS 5.4.1. Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC OCLK (OUTPUT) SDO SCKT LRCLK tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK) tlrckt = 3.5 + pad_timing (Cload_LRCCKT) - pad_timing (Cload_ OCLK) b) OCLK in input. OCLK (INPUT) ...
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... XTI,XTO and CLK_OUT timings XTI (INPUT) XTO t xto CLK_OUT t clk_out txto = 1.40 + pad_timing (Cload_XTO) ns 5.4.5. RESET The Reset min duration (t_reset_low_min) is 100ns RESET t t _biten _biten t t sckr_min_hi sckr_min_hi t sckr_min_period t t sdi_setup sdi_hold t t _src_hi _src_low reset_low_min STA003T t lo D98AU971 D98AU972 D98AU973 D98AU974 29/32 ...
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... The STA003T will use these parame- ters to derivate the register configurations for the other audio frequencies (32, 24, 16, 12, 8 KHz) according to the bistream informations. The STA003T DAC and PLL register must be configured according to the following steps: 1) OCLK_Freq determination from the DAC over- sampling factor O_FAC. ...
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... DIM. MIN. TYP. MAX. MIN. A 2.65 a1 0.1 0.3 0.004 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0 (typ.) D 17.7 18.1 0.697 E 10 10.65 0.394 e 1.27 e3 16.51 F 7.4 7.6 0.291 L 0.4 1.27 0.016 S 8 (max.) inch MECHANICAL DATA TYP. MAX. 0.104 0.012 0.019 0.013 0.020 0.713 0.419 0.050 0.65 0.299 0.050 STA003T OUTLINE AND SO28 31/32 ...
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... STA003T Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice ...