sta335bws13tr STMicroelectronics, sta335bws13tr Datasheet

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sta335bws13tr

Manufacturer Part Number
sta335bws13tr
Description
2.1-channel 40-watt High-efficiency Digital Audio System Sound Terminal?
Manufacturer
STMicroelectronics
Datasheet

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Features
March 2010
Wide-range supply voltage, 4.5 V to 21.5 V
Three power output configurations:
– 2 channels of ternary PWM
– 2 channels of ternary PWM
– 2.1 channels of binary PWM (left, right,
FFX with 100-dB SNR and dynamic range
Scalable FFX modulation index (up to 100%)
Selectable 32- to 192-kHz input sample rates
I
Digital gain/attenuation +48 dB to -80 dB with
0.125-dB/step resolution
Soft volume update with programmable ratio
Individual channel and master gain/attenuation
Two independent DRCs configurable as a
dual-band anti-clipper (B
independent limiters/compressors with
optional global DRC capability
EQ-DRC for DRC based on filtered signals
Dedicated LFE processing for bass boosting
with 0.125-dB/step resolution
Audio presets:
– 15 preset crossover filters
– 5 preset anti-clipping modes
– Preset night-time listening mode
Individual channel soft/hard mute
Independent channel volume and DSP bypass
I
Input and output channel mapping
2
2
C control with selectable device address
S input data interface
(2 x 20 W into 8 Ω at 18 V) + PWM output
(2 x 20 W into 8 Ω at 18 V) + ternary stereo
line-out
LFE) (2 x 9 W into 4 Ω +1 x 20 W into 8 Ω
at 18 V)
2.1-channel 40-watt high-efficiency digital audio system
2
DRC) or as
Doc ID 16861 Rev 3
Table 1.
STA369BWS
STA369BWSTR PowerSSO-36 EPD Tape and reel
Order code
Automatic invalid input-detect mute
Up to 8 user-programmable biquads/channel
Three coefficients banks for EQ presets storing
with fast recall via I
Extended filter dynamics +4/-4 for better sound
shaping and easier filter implementation
Bass/treble tones and de-emphasis control
Selectable high-pass filter for DC blocking
Advanced AM interference frequency
switching and noise suppression modes
F3X™ advanced PWM modulation scheme for
carrier suppression (headphone or line output)
Selectable high- or low-bandwidth
noise-shaping topologies
Selectable clock input ratio
96-kHz internal processing sample rate with
quantization error noise shaping for very low
cut-off frequency filters
Thermal overload and short-circuit protection
embedded
Video apps: 576 x f
PCB manufacturing short-circuit protection
technology
PowerSSO-36
with exposed pad down (EPD)
Device summary
PowerSSO-36 EPD Tube
Sound Terminal™
Package
2
S
C interface
STA369BWS
input mode supported
Packaging
www.st.com
1/89
89

Related parts for sta335bws13tr

sta335bws13tr Summary of contents

Page 1

Features Wide-range supply voltage, 4 21.5 V Three power output configurations: – 2 channels of ternary PWM ( into 8 Ω PWM output – 2 ...

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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STA369BWS 6.1 Configuration registers (addr 0x00 to 0x05 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 Volume ...

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Contents 6.7.8 6.8 Variable max power correction registers (addr 0x27 - 0x28 6.9 Distortion compensation registers (addr 0x29 - 0x2A ...

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STA369BWS 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STA369BWS List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables Table 49. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STA369BWS 1 Description The STA369BWS is an integrated solution of digital audio processing, digital amplifier controls and power output stage to create a high-power single-chip FFX digital amplifier with high-quality and high-efficiency. Three channels of FFX processing are provided. The ...

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Description volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio interference reduction modes. Dual-band DRC dynamically equalizes the system to provide linear frequency speaker response regardless of output power level. This feature separates ...

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STA369BWS 2 Pin connections 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (top view) GND_SUB TEST_MODE VCC_REG GND_REG OUT3B / FFX3B OUT3A / FFX3A 2.2 Pin description Table 2. Pin description Pin Type 1 GND ...

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Pin connections Table 2. Pin description (continued) Pin Type 11 Power 12 GND GND 15 Power I/O 21 Power 22 GND Power ...

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STA369BWS 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol V Power supply voltage (pins VCCx Digital supply voltage (pins VDD_DIG PLL supply voltage (pin VDD_PLL Operating junction temperature op ...

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Electrical specifications 3.3 Recommended operating conditions Table 5. Recommended operating condition Symbol V Power supply voltage (VCCxA, VCCxB Digital supply voltage DD_DIG V PLL supply voltage DD_PLL T Ambient temperature amb 3.4 Electrical specifications for the digital section ...

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STA369BWS 3.5 Electrical specifications for the power section The specifications given in this section are valid for the operating conditions kHz 384 kHz Table 7. Electrical specifications - power section Symbol Parameter ...

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Electrical specifications Figure 3. Test circuit Duty cycle = 50% INxY 16/89 OUTxY tr +Vcc M58 Ω OUTxY R 8 M57 gnd Doc ID 16861 Rev 3 STA369BWS VCC (0.9)*VCC ½VCC (0.1)*VCC t tf V67 + - vdc = Vcc/2 ...

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STA369BWS 3.6 Power on/off sequence Figure 4. Power-on sequence VCC VCC VCC VCC VCC VDD_Dig VDD_Dig VDD_Dig VDD_Dig VDD_Dig XTI XTI XTI XTI XTI Reset Reset Reset Reset Reset ...

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Processing data paths 4 Processing data paths Figure 6 and Figure 7 whole processing chain is composed of two consecutive sections. In the first one, dual-channel processing is implemented and in the second section each channel is fed into the ...

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STA369BWS In all the available configurations high-pass filtering with a 2-Hz cut-off frequency is applied before the postscale block. This filter cannot be disabled. Figure 7. Left and right processing, section 2 Dual-band DRC enabled ...

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I C bus specification bus specification The STA369BWS supports the I slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter ...

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STA369BWS 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA369BWS acknowledges this and then waits for the byte of internal address. After receiving the internal byte ...

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I C bus specification 5.4.4 Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA369BWS. The master acknowledges each data byte read and then ...

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STA369BWS 6 Register description Note: Addresses exceeding the maximum address number must not be written. Table 8. Register summary Addr Name D7 0x00 CONFA FDRB 0x01 CONFB C2IM 0x02 CONFC OCRB 0x03 CONFD SME 0x04 CONFE SVE 0x05 CONFF EAPD ...

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Register description Table 8. Register summary (continued) Addr Name D7 0x1F A1CF3 0x20 A2CF1 0x21 A2CF2 0x22 A2CF3 0x23 B0CF1 0x24 B0CF2 0x25 B0CF3 0x26 CFUD 0x27 MPCC1 0x28 MPCC2 0x29 DCC1 0x2A DCC2 0x2B FDRC1 0x2C FDRC2 0x2D STATUS ...

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STA369BWS Table 8. Register summary (continued) Addr Name D7 0x42 Reserved 0x43 Reserved 0x44 Reserved 0x45 Reserved 0x46 SHOK GND1A 0x47 Reserved 0x48 NSHAPE NSHXEN 0x49 CXTB4B1 CXTB4[1:0] 0x4A CXTB7B5 Reserved 0x4B MISC1 RPDNEN 0x4C MISC2 LPDP 0x4D BPTH 0x4E ...

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Register description 6.1 Configuration registers (addr 0x00 to 0x05) 6.1.1 Configuration register A (addr 0x00 FDRB TWAB 0 1 Master clock select Table 9. Master clock select Bit R/W 0 R/W 1 R/W 2 R/W The STA369BWS supports ...

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STA369BWS The STA369BWS has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation ...

Page 28

Register description Fault detect recovery bypass Table 15. Fault detect recovery bypass Bit R/W 7 R/W 0 The on-chip power block provides feedback to the digital controller which is used to indicate a fault condition (either overcurrent or thermal). When ...

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STA369BWS Table 18. Support serial audio input formats for MSB-first (SAIFB = 0) BICKI Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1) BICKI ...

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Register description Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1) (continued) BICKI make the STA369BWS work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It ...

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STA369BWS Channel input mapping Table 21. Channel input mapping Bit R R/W 1 Each channel received via I channel input mapping registers. This allows for flexibility in processing. The default settings of these registers maps each ...

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Register description Table 24. Compensating pulse size CSZ[3:0] 0000 0001 … 1111 Overcurrent warning adjustment bypass Table 25. Overcurrent warning bypass Bit R/W 7 R/W 1 The OCRB is used to indicate how STA369BWS behaves when an overcurrent warning condition ...

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STA369BWS De-emphasis Table 27. De-emphasis Bit R/W 1 R/W 0 DSP bypass Table 28. DSP bypass Bit R/W 2 R/W 0 Setting the DSPB bit bypasses the EQ function of the STA369BWS. Postscale link Table 29. Postscale link Bit R/W ...

Page 34

Register description Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the ...

Page 35

STA369BWS Setting the MPC bit turns on special processing that corrects the STA369BWS power device at high power. This mode should lower the THD full FFX system at maximum power output and slightly below. If enabled, MPC is ...

Page 36

Register description Zero-crossing volume enable Table 40. Zero-crossing volume enable Bit R/W RST 6 R/W 1 The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks are audible. Soft volume update enable Table 41. ...

Page 37

STA369BWS Table 43. Output configuration engine selection OCFG[1: Note: To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any ...

Page 38

Register description Figure 11. OCFG = 01 Figure 12. OCFG = 10 Figure 13. OCFG = 11 The STA369BWS can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot ...

Page 39

STA369BWS Figure 14. Output mapping scheme FFX ™ FFX ™ FFX ™ FFX ™ FFX ™ FFX ™ modulator modulator modulator modulator modulator modulator For each configuration the PWM signals from the digital driver are mapped in different ways to ...

Page 40

Register description 2.0 channels, two full-bridges (OCFG = 00) Mapping: FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B FFX4A -> OUT4A FFX4B -> OUT4B Default modulation: FFX1A/1B configured as ternary ...

Page 41

STA369BWS 2.1 channels, two half-bridges + one full-bridge (OCFG = 01) Mapping: FFX1A -> OUT1A FFX2A -> OUT1B FFX3A -> OUT2A FFX3B -> OUT2B FFX1A -> OUT3A FFX1B -> OUT3B FFX2A -> OUT4A FFX2B -> OUT4B Modulation: FFX1A/1B configured as ...

Page 42

Register description 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10) Mapping: FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B EAPD -> OUT4A TWARN -> OUT4B Default modulation: ...

Page 43

STA369BWS Invalid input detect mute enable Table 44. Invalid input detect mute enable Bit R/W 2 R/W 1 Setting the IDE bit enables this function, which looks at the input I mutes if the signals are perceived as invalid. Binary ...

Page 44

Register description The PWDN register is used to place the low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power-stage, ...

Page 45

STA369BWS 6.2.1 Mute/line output configuration register (addr 0x06 LOC1 LOC0 0 0 Table 50. Line output configuration LOC[1: Line output is only active when OCFG = 00. In this case LOC determines the line output ...

Page 46

Register description 6.2.5 Channel 3 / line output volume (addr 0x0A C3VOL7 C3VOL6 0 1 Table 52. Channel volume as a function of CxVOL[7:0] CxVOL[7:0] 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) … 01011111 (0x5F) 01100000 (0x60) 01100001 (0x61) ...

Page 47

STA369BWS 6.3 Audio preset registers (addr 0x0B and 0x0C) 6.3.1 Audio preset register 1 (addr 0x0B Reserved Reserved 1 0 Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configurations. ...

Page 48

Register description Table 55. Audio preset AM switching frequency selection (continued) AMAM[2:0] 101 110 Bass management crossover Table 56. Bass management crossover Bit R R/W 0 Table 57. Bass management ...

Page 49

STA369BWS 6.4 Channel configuration registers (addr 0x0E - 0x10 C1OM1 C1OM0 C2OM1 C2OM0 C3OM1 C3OM0 1 0 Tone control bypass Tone control (bass/treble) can be bypassed on a per channel ...

Page 50

Register description Binary output enable registers Each individual channel output can be set to output a binary PWM stream. In this mode output channel is considered the positive output and output B is negative inverse. Table 61. ...

Page 51

STA369BWS 6.5 Tone control register (addr 0x11 TTC3 TTC2 0 1 Tone control Table 64. Tone control boost/cut as a function of BTC and TTC bits BTC[3:0]/TTC[3:0] 0000 0001 0010 … 0101 0110 0111 1000 1001 … 1100 ...

Page 52

Register description 6.6.3 Limiter 2 attack/release rate (addr 0x14 L2A3 L2A2 0 1 6.6.4 Limiter 2 attack/release threshold (addr 0x15 L2AT3 L2AT2 0 1 6.6.5 Description The STA369BWS includes two independent limiter blocks. The purpose of ...

Page 53

STA369BWS release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the ...

Page 54

Register description Table 66. Limiter release rate vs LxR bits LxR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Anti-clipping mode Table 67. Limiter attack threshold vs LxAT bits (AC mode) LxAT[3:0] ...

Page 55

STA369BWS Table 67. Limiter attack threshold vs LxAT bits (AC mode) (continued) LxAT[3:0] 1110 1111 Table 68. Limiter release threshold vs LxRT bits (AC mode) LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 ...

Page 56

Register description Table 69. Limiter attack threshold vs LxAT bits (DRC mode) (continued) LxAT[3:0] 1001 1010 1011 1100 1101 1110 1111 Table 70. Limiter release threshold vs LxRT bits (DRC mode) LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 ...

Page 57

STA369BWS 6.6.7 Limiter 1 extended release threshold (addr 0x33 ERTHEN1 ERTH1[ The extended release threshold value is determined as follows: release threshold = -12 + ERTH1 / 4 6.6.8 Limiter 2 extended attack threshold (addr 0x34) ...

Page 58

Register description D7 D6 C1B7 C1B6 0 0 6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C C2B23 C2B22 C2B15 C2B14 C2B7 C2B6 0 0 6.7.4 Coefficient a1 data ...

Page 59

STA369BWS 6.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25 C5B23 C5B22 C5B15 C5B14 C5B7 C5B6 0 0 6.7.7 Coefficient read/write control register (addr 0x26 6.7.8 Description ...

Page 60

Register description Reading a coefficient from RAM 1. Select the RAM block with register 0x31 bit1, bit0. 2. Write 6-bits of address Write bit Read top 8-bits of coefficient in I ...

Page 61

STA369BWS Writing a set of coefficients to RAM 1. Select the RAM block with register 0x31 bit1, bit0. 2. Write 6-bits of starting address Write top 8-bits of coefficient Write middle 8-bits of ...

Page 62

Register description Table 71. RAM block for biquads, mixing, scaling, bass management (continued) Index Index (Hex) (Decimal) 40 0x28 41 0x29 42 0x2A 43 0x2B 44 0x2C 45 0x2D 46 0x2E 47 0x2F 48 0x30 49 0x31 50 0x32 51 ...

Page 63

STA369BWS Coefficients stored in the user defined coefficient RAM are referenced in the following manner: CxHy0 = b 1 CxHy1 = b 2 CxHy2 = -a 1 CxHy3 = -a 2 CxHy4 = b 0 where x represents the channel ...

Page 64

Register description 6.8 Variable max power correction registers (addr 0x27 - 0x28 MPCC15 MPCC14 MPCC7 MPCC6 1 1 MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in ...

Page 65

STA369BWS 6.11 Device status register (addr 0x2D PLLUL FAULT This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault ...

Page 66

Register description 6.12 EQ coefficients and DRC configuration register (addr 0x31 XOB Reserved RAM Table 73. EQ RAM select SEL[1: DRC / Anti clipping Bits AMGC[3:2] change the behavior of ...

Page 67

STA369BWS 6.13 Extended configuration register (addr 0x36 MDRC[1] MDRC[ Extended configuration register provides access to B 6.13.1 Dual-band DRC (B STA369BWS device provide a dual-band DRC (B path, as depicted in 2 Figure 19. B DRC ...

Page 68

Register description For the user programmable mode, use the formulae below to compute the high pass filters alpha -(1 + alpha where alpha = (1-sin(ω A first-order ...

Page 69

STA369BWS Figure 20. EQDRC scheme Channel In Channel In Channel In Channel In Channel In Channel In Channel In Channel In Extended postscale range Table 76. Bit PS48DB description PS48DB 0 1 Postscale is an attenuation by default. When PS48DB ...

Page 70

Register description Table 79. Bit BQ5 description BQ5 0 1 Table 80. Bit BQ6 description BQ6 0 1 Table 81. Bit BQ7 description BQ7 0 1 When filters from 5th to 7th are configured as user-programmable, the corresponding coefficients are ...

Page 71

STA369BWS When SVUPE = 1 the fade-in rate is defined by the SVUP[4:0] bits according to the following formula: Fade-in rate = dB/ms where N is the SVUP[4:0] value. Table 83. Bit SVDWE description SVDWE ...

Page 72

Register description 6.16 Extra volume resolution configuration registers (addr 0x3F VRESEN VRESTG 0 0 Extra volume resolution allows fine volume tuning in steps of 0.125 dB. The feature is enabled when VRESEN = 1, as depicted in volume ...

Page 73

STA369BWS Table 85. Bits VRESEN and VRESTG description VRESEN 6.17 Short-circuit protection mode registers SHOK (addr 0x46 GND1A GND1B 1 1 The following power-bridge pins short-circuit protection are implemented in STA369BWS: OUTxx vs GNDx ...

Page 74

Register description Figure 22. Short-circuit detection timing diagram (no short detected ...

Page 75

STA369BWS registers. D7 bit, when set, is responsible to activate this function on the crossover filter while the other bits address any specific biquads as per previous table. Channels 1 and 2 share the same settings. Bit D7 is effective ...

Page 76

Register description 6.20 Miscellaneous registers (addr 0x4B, 0x4C) 6.20.1 MISC1 (addr 0x4B RPDNEN NSHHPEN 0 0 Rate powerdown enable (RPDNEN) bit In STA369BWS, by default, powerdown pin and I perform the fadeout. This default can be changed so ...

Page 77

STA369BWS Figure 24. External active filter with connection for F3X output The two register bits work as per the following table. Table 87. F3X bits configuration F3X[1] 0 ...

Page 78

Register description 6.20.2 MISC2 (addr 0x4C LPDP LPD 0 0 External amplifier hardware pin enable (LPDP, LPD LPDE) bits Pin 32 (INT_LINE), described in using the following register settings, pin 32 can be reconfigured as the hardware pin ...

Page 79

STA369BWS Power down delay selector (PNDLSL[2:0]) bits As per Section , the assertion of PWDN activates a counter that, by default, after 13 million clock cycles puts the power bridge in tristate mode, independently from the fade out time. Using ...

Page 80

Register description 6.22 Bad PWM detection registers (addr 0x4D, 0x4E, 0x4F BPTH[5] BPTH[ BP4B BP4A BPTIM[7] BPTIM[ STA369BWS implements a detection on PWM outputs which is able to ...

Page 81

STA369BWS 6.23.2 XCCHKE registers (addr 0x63 - 0x65 XCCHKE[7] XCCHKE[ XCCHKE[15] XCCHKE[14 XCCHKE[23] XCCHKE[22 6.23.3 BQCHKR registers (addr 0x66 - 0x68 BQCHKR[7] BQCHKR[ ...

Page 82

Register description 6.23.6 Description STA369BWS implements an automatic CRC computation for the Biquad and MDRC / XOver coefficient memory bit XORed to obtain BQCHKE checksum, while cells from 0x28 to 0x31 are XORed to obtain the XCCHKE checksum. Both checksum ...

Page 83

STA369BWS 7 Applications 7.1 Applications schematic Figure 27 below shows the typical applications schematic for STA369BWS. Special attention has to be paid to the layout of the PCB. All the decoupling capacitors have to be placed as close as possible ...

Page 84

... Applications 7.3 Typical output configuration Figure 28 shows the typical output configuration used for BTL stereo mode. Please contact STMicroelectronics for other recommended output configurations. Figure 28. Output configuration for stereo BTL mode (R OUT1A OUT1A OUT1A OUT1B OUT1B OUT1B OUT2A OUT2A OUT2A OUT2B OUT2B ...

Page 85

STA369BWS 8 Package thermal characteristics Using a double-layer PCB the thermal resistance, junction to ambient, with 2 copper ground areas The dissipated power within the device depends primarily on the supply voltage, load impedance and ...

Page 86

Package mechanical data 9 Package mechanical data Figure 30 shows the package outline and Figure 30. PowerSSO-36 EPD outline drawing 86/89 Table 90 gives the dimensions. Doc ID 16861 Rev 3 STA369BWS ...

Page 87

STA369BWS Table 90. PowerSSO-36 EPD dimensions Symbol Min A 2.15 A2 2.15 a1 0.00 b 0.18 c 0.23 D 10. 10. 0. ...

Page 88

Revision history 10 Revision history Table 91. Document revision history Date 11-Dec-2009 10-Feb-2010 01-Mar-2010 88/89 Revision 1 Initial release. 2 Removed preliminary banner - datasheet now final Added Rth j-amb typical value to Added Section 3.6: Power on/off sequence on ...

Page 89

... STA369BWS Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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