sta33013tr STMicroelectronics, sta33013tr Datasheet

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sta33013tr

Manufacturer Part Number
sta33013tr
Description
2.0 Digital Audio Processor With Ffx Digital Modulator And Analog And Digital Inputs
Manufacturer
STMicroelectronics
Datasheet
Features
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Table 1.
December 2007
STA330
STA33013TR
Up to 96 dB dynamic range
Sample rates from 8 kHz to 192 kHz
FFX (digital modulation) class-D driver
Digital supply voltage from 1.5 V to 3.6 V
Analog supply voltage from 1.5 V to 3.6 V
18-bit audio processing
and class-D FFX digital modulator
100-dB SNR analog to digital converter
Digital volume control:
– +36 dB to -105 dB in 0.5 dB steps
– Software volume update
Individual channel and master gain/attenuation
Automatic invalid-input detect mute
Order code
Device summary
with FFX digital modulator and analog and digital inputs
VFQFPN52
VFQFPN52
Package
Rev 1
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2-channel serial input/output data interface
Digitally controlled pop-free operation
2.0 digital audio processor
Tube
Tape and reel
VFQFPN52
Packaging
STA330
www.st.com
1/55
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sta33013tr Summary of contents

Page 1

... Software volume update ! Individual channel and master gain/attenuation ! Automatic invalid-input detect mute Table 1. Device summary Order code STA330 STA33013TR December 2007 2.0 digital audio processor ! 2-channel serial input/output data interface ! Digitally controlled pop-free operation Package VFQFPN52 VFQFPN52 ...

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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STA330 8.2 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Introduction 1 Introduction The STA330 is a digital stereo audio processor with analog and digital input. It includes an audio DSP and FFX proprietary high-efficiency class-D driver. In conjunction with a power device, the STA330 provides high-quality digital ...

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STA330 2 Connection diagrams and pin descriptions 2.1 Connection diagram Figure 2. Pin out (package underside view Connection diagrams and pin descriptions 27 VFQFPN52 Exposed pad down Exposed pad 5/55 ...

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Connection diagrams and pin descriptions 2.2 Pin description Table 2. Pin list Pin # Name 1 STBY 2 INL 3 INR 4 VBIAS 5 AVDD 6 VHI 7 VLO 8 AGND 9 VCM 10 RST_N 11 CLKOUT 12 GND1 13 ...

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STA330 Table 2. Pin list (continued) Pin # Name POWERFAULT/ 31 EAPD I2CDIS 34 SCL 35 SDA 36 SELCLK33 37 MCLK33 38 XTI 39 XTO 40 FILT 41 GNDPLL 42 VDDPLL 43 GND2 44 VDD2 45 SDATAI ...

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Electrical specifications 3 Electrical specifications 3.1 Maximum and recommended operating conditions Table 3 gives the maximum ratings and Table 3. Absolute maximum ratings Symbol VDD/VDD1/VDD2 AVDD VDDPLL VCC1A/1B/2A/2B VCC33 VDDIO STG T AMB ...

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STA330 3.2 Electrical characteristics Table 5 lists the device electrical characteristics under the conditions nominal supply voltage (see Table 4), LRCLKI frequency (f unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Logic power supply current at IstbyL standby Logic ...

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Electrical specifications 3.3 Lock time Table 6 gives the typical lock time of the PLL using the suggested loop filter 1.8-V supply and 30 Table 6. PLL lock time Lock time 3.4 ADC performance values Table 7. Programmable gain performance ...

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STA330 4 Applications Figure 3 to Figure 6 STA510F. Figure 3. STA330 codec block Figure 4. STA510F power stage block below show the circuit diagrams of a typical application with the IC401 IC - STA510F Applications PWM output selection Binary, ...

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Applications Figure 5. Connector and power supply block Figure 6. Direct control and settings block Table 8. Components for setting up application Component R413 R28 R12 R21 R11 R18 R17 12/55 µController µLess No Yes Yes No Yes Yes No ...

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STA330 Table 8. Components for setting up application (continued) Component R25 R16 R22 µController µLess No No Yes Yes No No 2-3 1-2 2-3 1-2 2-3 2-3 2-3 (L) 1-2 (H) Applications Comments STA510F: PWM2A Volume ...

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Digital processing 5 Digital processing The STA330 processor block is a digital block providing two channels of audio processing and channel-mapping capability. 5.1 Signal processing flow stereo ADC data can be selected. The I ADC sampling ...

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STA330 5.3 Volume control and gain The volume control structure of the STA330 consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are ...

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PLL 6 PLL Figure 7 shows the main components of the PLL. Figure 7. PLL block diagram CLKIN IDF INFOUT REFOUT STRB STRB_ BYPASS FRAC_CTRL DITHER_DISABLE 16/55 INFIN Input frequency FBCLK divider INFIN Phase / frequency Buffer divider (PFD) FBCLK ...

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STA330 6.1 Functional description Phase/frequency detector The phase/frequency detector (PFD) compares the phase difference between the corresponding rising edges of INFIN and FBCLK, (clock output from the loop frequency divider) by generating voltage pulses with widths proportional to the input ...

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PLL PLL filter Figure 8 shows the PLL filter scheme. Recommended values are R1 = 12.5 kΩ 250 pF, and pF. Figure 8. PLL filter scheme Table 6 on page 10 6.2 Configuration examples The ...

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STA330 If register bit PLLCFG0.FRAC_CTRL = 0, then VCO INFIN PHI VCO In the above equations: FRACT = Decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0] IDF = Input division factor (refer to previous formulas) LDF ...

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PLL In the following examples floor means rounded towards zero and round means rounded to nearest integer. Example MHz XTI f = 44.1 kHz S IDF should be equal to 3 otherwise LDF become less than ...

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STA330 7 Analog-digital converter (ADC) 7.1 Functional description The STA330 analog input is provided through a low-power, low-voltage, stereo, audio-ADC front end designed for audio applications. It includes a programmable gain amplifier, anti- aliasing filter, a low-noise microphone biasing circuit, ...

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Analog-digital converter (ADC) 7.1.2 High-pass filter characteristics Table 13. High-pass filter characteristics Frequency response -0.08 dB Phase deviation Pass-band ripple 7.1.3 Programmable gain amplifier The programmable gain amplifier (PGA) is available in mic-in mode only. ...

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STA330 7.3 Configuration examples The ADC sampling frequency can be selected from three values: " normal (from 32 kHz to 48 kHz) " low (from 16 kHz to 24 kHz) " very-low (from 8 kHz to 12 kHz). The setting ...

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Serial digital audio interface (SAI) 8 Serial digital audio interface (SAI) 8.1 Specifications The serial-to-parallel interface and the parallel-to-serial interface can have different sampling rates. The following terms are used in this section: " BICLK active edge: Pins SDATAI, SDATAO, ...

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STA330 8.3 Slave mode In this mode, pins BICLKI/O and pins LRCLKI/O are configured as inputs. Figure 11. Slave mode BICLKI/ BICLKO LRCLKI/ LRCLKO SDATAO SDATAI Table 15. Slave mode Symbol t BICLK cycle time BCY t BICLK pulse width ...

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Serial digital audio interface (SAI) 8.4 Serial formats Different audio formats are supported in both master and slave modes. Clock and data configurations can be customized to match most of the serial audio protocols available on the market. Data length ...

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STA330 8.4.1 DSP Figure 14. DSP LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 2 8.4 Figure 15 LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO Left ...

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Serial digital audio interface (SAI) 8.4.3 PCM/IF (non-delayed mode) " MSB first " 16-bit data Figure 16. PCM/IF (non-delayed mode) LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI SDATAO 8.4.4 PCM/IF (delayed mode) " MSB first " 16-bit data Figure ...

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STA330 8.5 SAI pass-through A configuration is available which allows the SAI input signal to be passed straight to the digital output. The STA330 is able to translate the incoming serial audio interface signal from SAI- different output ...

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I C interface interface This section describes the communication protocol of the I 9.1 Data transition and change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition ...

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STA330 9.6 Write operation Following the start condition the master sends a device select code with the R/W bit set to 0. The STA330 acknowledges this and the writes to the byte of the internal address. After receiving the internal ...

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I C interface 9.7.4 Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA330. The master acknowledges each data byte read and then generates ...

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STA330 10 Registers 10.1 Summary Table 16. Register summary Address Name Bit 7 0x00 FFXCFG0 MUTE 0x01 FFXCFG1 L1_R2 0x02 MVOL 0x03 LVOL 0x04 RVOL 0x05 TTF0 0x06 TTF1 0x07 TTP0 0x08 TTP1 BICLK_ 0x0A S2PCFG0 STRB 0x0B S2PCFG1 PDATA_LENGTH[1:0] ...

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Registers Table 16. Register summary (continued) Address Name Bit 7 0x2A BISTST1 0x2B BISTST2 0x2D PWMINT1 0x2E PWMINT2 POWER 0x32 POWST DOWN 10.2 General registers FFXCFG0 Bit 7 Bit 6 MUTE POW_STBY SOFT_VOL_ON Address: 0x00 Type: R/W Buffer: No Reset: ...

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STA330 FFXCFG1 Bit 7 Bit 6 MUTE_ON_ L1_R2 INVALID Address: 0x01 Type: R/W Buffer: No Reset: 0xF8 Description: 7 L1_R2: channel mapping: 0: right channel is mapped to output channel 1 and left channel is mapped to output channel 2 ...

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Registers LVOL Bit 7 Bit 6 Address: 0x03 Type: R/W Buffer: No Reset: 0x48 Description: 7:0 SET_VOL_LEFT[7:0]: left channel volume control: Left channel volume control (from + -91 0.5 dB steps) Default value (0x48) corresponds to ...

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STA330 TTF0 Bit 7 Bit 6 Address: 0x05 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 MSBs of TIM_TS_FAULT[15:0]: See TTF1 on page TTF1 Bit 7 Bit 6 Address: 0x06 Type: R/W Buffer: No Reset: 0x02 Description: 7:0 LSBs of ...

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Registers TTP0 Bit 7 Bit 6 Address: 0x07 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 MSBs of TIM_TS_POWUP[15:0]: See register TTP1. TTP1 Bit 7 Bit 6 Address: 0x08 Type: R/W Buffer: No Reset: 0x02 Description: 7:0 LSBs of TIM_TS_POWUP[15:0]: ...

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STA330 S2PCFG0 Bit 7 Bit 6 BICLK_STRB LRCLK_LEFT SHARE_BILR Address: 0x0A Type: R/W Buffer: No Reset: 0xD2 Description: 7 BICLK_STRB: 0: bit clock strobe edge is falling edge, bit clock active edge is rising edge 1: bit clock strobe edge ...

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Registers S2PCFG1 Bit 7 Bit 6 PDATA_LENGTH[1:0] Address: 0x0B Type: R/W Buffer: No Reset: 0x91 Description: 7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: 24 bits (default) Length is (N+ bit 5:4 BICLK_OS[1:0]: bit clock oversampling: 01: ...

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STA330 P2SCFG0 Bit 7 Bit 6 BICLK_ STRB LRCLK_LEFT SDATAO_ACT Address: 0x0C Type: R/W Buffer: No Reset: 0xD3 Description: 7 BICLK_STRB: defines the bit clock edges: 0: strobe is falling edge, active edge is rising 1: strobe is rising edge, ...

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Registers P2SCFG1 Bit 7 Bit 6 PDATA_LENGTH[1:0] Address: 0x0D Type: R/W Buffer: No Reset: 0x91 Description: 7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: 24 bits (default) Length is (PDATA_LENGTH + bit 5:4 BICLK_OS[1:0]: bit clock oversampling: 01: ...

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STA330 PLLCFG0 Bit 7 Bit 6 PLL_DIRECT_ FRAC_CTRL PROG Address: 0x14 Type: R/W Buffer: No Reset: 0x00 Description: 7 PLL_DIRECT_PROG: PLL programming: 0: default 1: PLL is programmed according to the PLLCFG register settings 6 FRAC_CTRL: 0: default 1: PLL ...

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Registers PLLCFG2 Bit 7 Bit 6 Address: 0x16 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 FRAC_INPUT[7:0]: 16 bits are used to set the fractional part of PLL multiplication factor PLLCFG3 Bit 7 Bit 6 STRB STRB_BYPASS Address: 0x17 Type: ...

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STA330 PLLPFE Bit 7 Bit 6 PLL_BYP_UNL BICLK2PLL PLL_PWDN Address: 0x18 Type: R/W Buffer: No Reset: 0x00 Description: 7 PLL_BYP_UNL: PLL bypass: 0: PLL is not bypassed (default) 6 BICLK2PLL: 0: default 5 PLL_PWDN: 0: default 4 PFE1A: 0: default ...

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Registers PLLST Bit 7 Bit 6 PLL_ PLL_UNLOCK PWD_ STATE BYP_ STATE Address: 0x19 Type: RO Buffer: No Reset: Undefined Description: 7 PLL_UNLOCK: PLL unlock state: 0: PLL is not in unlock state 6 PLL_PWD_ STATE: PLL power-down state: 0: ...

Page 47

STA330 ADCCFG Bit 7 Bit 6 PGA[2:0] Address: 0x1E Type: RO Buffer: No Reset: Undefined Description: 7:5 PGA[2:0]: gain selection bits for the ADC programmable gain amplifier: 000: default Values are from steps ...

Page 48

Registers MISC Bit 7 Bit 6 OSC_DIS P2P_FS_RANGE[2:0] Address: 0x20 Type: R/W Buffer: No Reset: 0x21 Description: 7 OSC_DIS: enable/disable crystal oscillator: 0: default 6:4 P2P_FS_RANGE[2:0]: FFX audio frequency range: 000: very low (f 001: low (f s 010: normal ...

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STA330 FFXST Bit 7 Bit 6 Address: 0x23 Type: RO Buffer: No Reset: Undefined Description: 7:3 Reserved 2 INVALID_INP_FBK: invalid input status: 1: invalid input sent to FFX 1 MUTE_INT_FBK: FFX mute status 1: FFX is in mute state 0 ...

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Registers POWST Bit 7 Bit 6 POW_ POW_ POW_FAULT1A POWERDOWN TRISTATE Address: 0x32 Type: RO Buffer: No Reset: Undefined Description: 7 POW_POWERDOWN: power-down bridge: 0: not in power-down state 6 POW_TRISTATE: 1: power bridge is in tri-state 5 POW_FAULT1A: 1: ...

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STA330 11 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These package have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner ...

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Package information Table 17. VFQFPN52 dimensions Reference ddd 52/55 Dimensions in mm Min Typical Max 0.800 0.900 1.000 0.020 0.050 0.650 1.000 0.250 0.180 0.230 0.300 7.875 8.000 8.125 ...

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... STA330 12 Trademarks and other acknowledgements FFX is a STMicroelectronics proprietary digital modulation technology. ECOPACK is a registered trademark of STMicroelectronics. Trademarks and other acknowledgements 53/55 ...

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Revision history 13 Revision history Table 18. Document revision history Date 12-Dec-2007 54/55 Revision 1 Initial release STA330 Changes ...

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... STA330 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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