sta339bw STMicroelectronics, sta339bw Datasheet

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sta339bw

Manufacturer Part Number
sta339bw
Description
2.1-channel High-efficiency Digital Audio System
Manufacturer
STMicroelectronics
Datasheet

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Features
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Table 1.
May 2009
STA339BW
STA339BW13TR
Wide voltage supply range
– 5 V to 26 V (operating range)
– 30 V (absolute maximum rating)
3 power output configurations
– 2 channels of ternary PWM (stereo mode)
– 3 channels - left, right using binary and LFE
– 2 channels of ternary PWM (2 x 20 W) +
2.1 channels of 24-bit FFX
dynamic range
Selectable 32 to 192 kHz input sample rates
I
Digital gain/attenuation +48 dB to -80 dB with
0.5 dB/step resolution
Soft volume update with programmable ratio
Individual channel and master gain/attenuation
Two independent DRC configurable as a dual-
band anti-clipper (B
limiters/compressors
EQ-DRC for DRC based on filtered signals
Dedicated LFE processing for bass boosting
with 0.5 dB/step resolution
Audio presets:
– 15 preset crossover filters
– 5 preset anti-clipping modes
– Preset night-time listening mode
Individual channel and master soft/hard mute
2
C control with selectable device address
(2 x 20 W into 8 Ω at 18 V)
using ternary PWM (2.1 mode) (2 x 9 W +
1 x 20 W into 2 x 4 Ω, 1 x 8 Ω at 18 V)
stereo lineout ternary
Order code
Device summary
2
DRC) or independent
®
2.1-channel high-efficiency digital audio system
100 dB SNR and
PowerSSO-36 slug down
PowerSSO-36 slug down
Doc ID 15251 Rev 4
Package
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Independent channel volume and DSP bypass
Automatic zero-detect mute
Automatic invalid input-detect mute
2-channel I
Input and output channel mapping
Up to 8 user-programmable biquads per
channel with 28-bit resolution
3 coefficient banks for EQ presets storing with
fast recall via I
Bass/treble tones and de-emphasis control
Selectable high-pass filter for DC blocking
Advanced AM interference frequency
switching and noise suppression modes
Selectable high- or low-bandwidth
noise-shaping topologies
Variable max power correction for lower
full-power THD
Selectable clock input ratio
96 kHz internal processing sample rate, 24 to
28-bit precision
Thermal overload and short-circuit protection
embedded
Video apps: 576 * f
Fully compatible with STA339BWS.
PowerSSO-36 (slug down)
2
S input data interface
Tube
Tape and reel
2
C interface
S
input mode supported
STA339BW
Packaging
www.st.com
1/77
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Related parts for sta339bw

sta339bw Summary of contents

Page 1

... Selectable clock input ratio ! 96 kHz internal processing sample rate 28-bit precision ! Thermal overload and short-circuit protection embedded ! Video apps: 576 * f ! Fully compatible with STA339BWS. Package PowerSSO-36 slug down PowerSSO-36 slug down Doc ID 15251 Rev 4 STA339BW PowerSSO-36 (slug down input data interface 2 ...

Page 2

... C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 5.1.2 5.1.3 5.1.4 5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.1 5.3.2 5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.1 5.4.2 5.4.3 2/77 Functional pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 15251 Rev 4 STA339BW ...

Page 3

... STA339BW 5.4.4 5.4.5 5.4.6 6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 Configuration register A (addr 0x00 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 Configuration register B (addr 0x01 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 Configuration register C (addr 0x02 6.3.1 6.3.2 6.3.3 6.4 Configuration register D (addr 0x03 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.5 Configuration register E (addr 0x04 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Thermal warning adjustment bypass ...

Page 4

... Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Limiter 1 Extended attack threshold (addr 0x32 Doc ID 15251 Rev 4 STA339BW ...

Page 5

... STA339BW 6.11.6 6.11.7 6.11.8 6.12 User-defined coefficient control registers (addr 0x16 - 0x26 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.12.7 6.12.8 6.12.9 6.12.10 Coefficient a1 data register bits 7 6.12.11 Coefficient a2 data register bits 23: 6.12.12 Coefficient a2 data register bits 15 6.12.13 Coefficient a2 data register bits 7 6.12.14 Coefficient b0 data register bits 23: 6.12.15 Coefficient b0 data register bits 15 6.12.16 Coefficient b0 data register bits 7 6.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.12.18 User-defined ...

Page 6

... Contents 6.19 EQ soft volume configuration registers (addr 0x37 - 0x38 6.20 DRC RMS filter coefficients (addr 0x39 - 0x3E Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.1 Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.2 PLL filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6/77 Doc ID 15251 Rev 4 STA339BW ...

Page 7

... STA339BW List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Thermal data Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Functional pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Register summary Table 10. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11 ...

Page 8

... Extended attack rate setup for limiter Table 80. De-emphasis filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 81. Bass filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 82. Treble filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 83. Soft volume (increasing) setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 84. Soft volume (decreasing) setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 85. PowerSSO-36 slug down dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 86. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8/77 Doc ID 15251 Rev 4 STA339BW ...

Page 9

... STA339BW List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2. Pin connection PowerSSO-36 (top view Figure 3. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4. Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. Test circuit Figure 6. Test circuit Figure 7. Left and right processing part Figure 8. Processing part Figure 9. ...

Page 10

... W provided by the device and external power for FFX power drive. Also provided in the STA339BW are a full assortment of digital processing features. This includes programmable 28-bit biquads (EQ) per channel and bass/treble tone control. Available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions ...

Page 11

... STA339BW 1.1 Block diagram Figure 1. Block diagram interface Volume control PLL Digital DSP Protection current/thermal Power control FFX Regulators Doc ID 15251 Rev 4 Channel 1A Channel 1B Logic Channel 2A Channel 2B Bias Power Description 11/77 ...

Page 12

... Power positive supply OUT2A Output half bridge 2A OUT1B Output half bridge 1B Doc ID 15251 Rev 4 36 VDD_DIG 35 GND_DIG 34 SCL 33 SDA 32 INT_LINE 31 RESET 30 SDI 29 LRCKI 28 BICKI 27 XTI 26 GND_PLL 25 FILTER_PLL VDD_PLL 24 PWRDN 23 GND_DIG 22 VDD_DIG 21 20 TWARN / OUT4A 19 EAPD / OUT4B D05AU1638 Description - 3 reference CC STA339BW ...

Page 13

... STA339BW Table 2. Pin description (continued) Pin Type 11 Power 12 GND GND 15 Power I/O 21 Power 22 GND Power GND I GND 36 Power Name VCC1 Power positive supply GND1 Power negative supply ...

Page 14

... In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded. Parameter (1) Doc ID 15251 Rev 4 STA339BW Min Typ Max -0 -0.3 ...

Page 15

... STA339BW 3.3 Recommended operating conditions Table 5. Recommended operating condition Symbol V Power supply voltage (VCCxA, VCCxB) CC VDD_DIG Digital supply voltage VDD_PLL PLL supply voltage T Ambient temperature amb 3.4 Electrical specifications for the digital section Table 6. Electrical specifications - digital section Symbol Low-level input current without ...

Page 16

... Doc ID 15251 Rev 4 Min Typ Max - 180 250 ( ( ( ( 0 3.0 3.8 4.0 3.8 4 3.5 4 100 - - 100 - - STA339BW = Unit W W mΩ µ ...

Page 17

... STA339BW Table 7. Electrical specifications - power section (continued) Symbol Parameter THD+N Total harmonic distortion + noise X Crosstalk TALK Peak efficiency, FFX mode η Peak efficiency,binary modes 1. Refer to Figure 5: Test circuit 1. 2. Limit current if the register (OCRB par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. When disabled refer to the Isc ...

Page 18

... Don’t care Don’t care 2 C program, sequence start: 1ms - f < 1 MHz. max min gives information on setting up the Don’t care Don’t care Doc ID 15251 Rev 4 STA339BW CMD0 CMD0 CMD0 CMD0 CMD0 CMD1 CMD1 CMD1 CMD1 ...

Page 19

... STA339BW 3.7 Testing 3.7.1 Functional pin definition Table 8. Functional pin definition Pin name Number PWRDN 23 TWARN 20 EAPD 19 Figure 5. Test circuit 1 Duty cycle = 50% Figure 6. Test circuit 2 Duty cycle=A M58 DTin(A) INA M57 Logic value 0 Low consumption 1 Normal operation A temperature warning is indicated by the external power ...

Page 20

... Biquad Biquad Biquad Biquad Biquad Biquad Biquad Biquad Bass Bass Treble Treble De-Emph. De-Emph C2TCB=0 If C2TCB=0 If DEMP=0 If DEMP=0 BTC: bass boost/cut BTC: bass boost/cut TTC: treble boost/cut TTC: treble boost/cut STA339BW Figure 8 ...

Page 21

... STA339BW Figure 8. Processing part 2 Dual-band DRC enabled Dual-band DRC disabled Volume Volume C1Mx1 = C1Mx1 = C1Mx1 C1Mx1 0x7FFFFF 0x7FFFFF Hi-Pass Hi-Pass DRC DRC + + + + Filter Filter Hi-pass Hi-pass - - - filter filter + + + Volume Volume ...

Page 22

... The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA339BW is always a slave device in all of its communications. It can operate 400 kb/s (fast-mode bit rate). The STA339BW I 5 ...

Page 23

... Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA339BW acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA339BW again responds with an acknowledgement. ...

Page 24

... SUB-ADDR DEV-ADDR RW START RW RW= ACK ACK ACK HIGH DATA DATA ACK ACK ACK SUB-ADDR DEV-ADDR RW START RW Doc ID 15251 Rev 4 STA339BW ACK DATA IN STOP ACK ACK DATA IN DATA IN NO ACK DATA STOP NO ACK DATA STOP ACK ACK DATA DATA DATA STOP NO ACK ...

Page 25

... STA339BW 6 Register description Table 9. Register summary Addr Name D7 0x00 CONFA FDRB 0x01 CONFB C2IM 0x02 CONFC OCRB 0x03 CONFD SME 0x04 CONFE SVE 0x05 CONFF EAPD 0x06 MUTE/LOC LOC1 0x07 MVOL MV7 0x08 C1VOL C1V7 0x09 C2VOL C2V7 0x0A C3VOL C3V7 ...

Page 26

... SVDW[4] R_C0[22] R_C0[21] R_C0[20] R_C0[14] R_C0[13] R_C0[12] R_C0[6] R_C0[5] R_C0[4] R_C1[22] R_C1[21] R_C1[20] R_C1[14] R_C1[13] R_C1[12] R_C1[6] R_C1[5] R_C1[4] Doc ID 15251 Rev 4 STA339BW C4B19 C4B18 C4B17 C4B11 C4B10 C4B9 C4B3 C4B2 C4B1 C5B19 C5B18 C5B17 C5B11 C5B10 C5B9 C5B3 C5B2 ...

Page 27

... R/W 0 R/W 1 R/W 2 R/W The STA339BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is: " 32.768 MHz for 32 kHz " 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz " 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz ...

Page 28

... Thermal warning adjustment bypass Table 15. Thermal warning adjustment bypass Bit R/W 6 R/W 1 The on-chip STA339BW power output block provides feedback to the digital controller using inputs to the power control block. Input TWARN is used to indicate a thermal warning 28/77 RST Name Selects internal interpolation ratio based on input [1:0] ...

Page 29

... R/W 0 The on-chip STA339BW power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting which directs the power output block to begin recovery), holds for period of time in the range of 0 ...

Page 30

... Serial data interface The STA339BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA339BW always acts as slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12 ...

Page 31

... Supported serial audio input formats for LSB-first (SAIFB = 1) BICKI make the STA339BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that: ! the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on the settings in ! the PLL must be locked ...

Page 32

... Processing channel 1 receives Right I 0: Processing channel 2 receives Left I C2IM 1: Processing channel 2 receives Right can be mapped to any internal processing channel via the 2 S input channel to its corresponding processing Doc ID 15251 Rev 4 STA339BW 2 C configuration should be issued 2 C operation due Description 2 S master devices Description ...

Page 33

... STA339BW 6.3 Configuration register C (addr 0x02 OCRB Reserved 1 0 6.3.1 FFX power output mode Table 23. FFX power output mode Bit R R/W 1 The FFX power output mode selects how the FFX output timing is configured. Different power devices use different output modes. Table 24. ...

Page 34

... High-pass filter bypass Bit R/W 0 R/W 0 The STA339BW features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a FFX amplifier. DC signals can cause speaker damage. When HPB = 0, this filter is enabled. 6.4.2 De-emphasis Table 29. ...

Page 35

... STA339BW 6.4.4 Post-scale link Table 31. Post-scale link Bit R/W 3 R/W 0 Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster. 6.4.5 Biquad coefficient link Table 32 ...

Page 36

... R/W 1 Setting the MPC bit turns on special processing that corrects the STA339BW power device at high power. This mode should lower the THD full FFX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the line- out channels ...

Page 37

... R/W 0 STA339BW features aFFX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an AM tuner active. The SNR of the FFX processing is reduced to approximately this mode, which is still greater than the SNR of AM radio. ...

Page 38

... ECLE LDTE 0 1 RST Name OCFG0 Selects the output configuration OCFG1 Output configuration Binary 0 ° Binary 90° Binary 0° Binary 90° w/ C3BO 45° w/ C3BO 45° Doc ID 15251 Rev BCLE IDE OCFG1 Description Config pin STA339BW D0 OCFG0 0 ...

Page 39

... STA339BW Figure 11. OCFG = 00 (default value) Figure 12. OCFG = 01 Figure 13. OCFG = 10 OUT1A Half Bridge Channel 1 Half Bridge OUT1B OUT2A Half Bridge Channel 2 Half Bridge OUT2B OUT3A LineOut 1 LPF OUT3B OUT4A LineOut 2 LPF OUT4B Half Channel 1 Bridge OUT1A Half Channel 2 Bridge OUT1B OUT2A Half ...

Page 40

... Register description Figure 14. OCFG = 11 The STA339BW can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always fs) seconds length. The PWM slot define the maximum extension for PWM rise and fall edge, that is, rising edge as far as the falling edge cannot range outside PWM slot boundaries ...

Page 41

... STA339BW 2.0 channels, two full bridges (OCFG = 00) " FFX1A -> OUT1A " FFX1B -> OUT1B " FFX2A -> OUT2A " FFX2B -> OUT2B " FFX3A -> OUT3A " FFX3B -> OUT3B " FFX4A -> OUT4A " FFX4B -> OUT4B " FFX1A/1B configured as ternary " FFX2A/2B configured as ternary " FFX3A/3B configured as lineout ternary " ...

Page 42

... PWM are replicated. In this configuration the PWM slot phase is the following as shown in Figure 17. 2.1 channels (OCFG = 01) PWM slots 42/77 OUT1A OUT1A OUT1B OUT1B OUT2A OUT2A OUT2B OUT2B OUT3A OUT3A OUT3B OUT3B OUT4A OUT4A OUT4B OUT4B Doc ID 15251 Rev 4 STA339BW Figure 17. ...

Page 43

... STA339BW 2.1 channels, two fullbridge + one external full bridge (OCFG = 10) " FFX1A -> OUT1A " FFX1B -> OUT1B " FFX2A -> OUT2A " FFX2B -> OUT2B " FFX3A -> OUT3A " FFX3B -> OUT3B " EAPD -> OUT4A " TWARN -> OUT4B " FFX1A/1B configured as ternary " FFX2A/2B configured as ternary " ...

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... Binary output mode clock loss detection enable RST Name LDTE LRCLK double trigger protection enable RST Name ECLE Auto EAPD on clock loss RST Name 0: IC power down low-power condition PWDN 1: IC normal operation Doc ID 15251 Rev 4 STA339BW Description 2 S data and automatically Description Description Description Description ...

Page 45

... STA339BW 6.6.7 External amplifier power down Table 51. External amplifier power down Bit R/W 7 R/W 0 The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed on a low-power state (disabled). This register also controls the FFX4B/EAPD output pin when OCFG = 10. ...

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... C3V7 C3V6 0 1 The Volume structure of the STA339BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5 dB steps from + dB example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB ...

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... STA339BW Table 54. Channel volume as a function of CxV[7:0] (continued) CxV[7:0] 01100001 (0x61) … 11010111 (0xD7) 11011000 (0xD8) 11011001 (0xD9) 11011010 (0xDA) … 11101100 (0xEC) 11101101 (0xED) … 11111111 (0xFF) 6.8 Audio preset registers (addr 0x0B and 0x0C) 6.8.1 Audio preset register 1 (addr 0x0B ...

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... Hz 240 Hz Doc ID 15251 Rev 4 Description 44.1 kHz/88.2 kHz input fs 0.535 MHz - 0.670 MHz 0.671 MHz - 0.800 MHz 0.801 MHz - 1.000 MHz 1.001 MHz - 1.180 MHz 1.181 MHz - 1.340 MHz 1.341 MHz - 1.500 MHz 1.501 MHz - 1.700 MHz Description Crossover frequency STA339BW ...

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... STA339BW Table 59. Bass management crossover frequency (continued) XO[3:0] 1010 1011 1100 1101 1110 1111 6.9 Channel configuration registers (addr 0x0E - 0x10 C1OM1 C1OM0 C2OM1 C2OM0 C3OM1 C3OM0 1 0 6.9.1 Tone control bypass Tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2. ...

Page 50

... Channel output mapping as a function of CxOM bits CxOM[1: 50/77 FFX 3-state output - normal operation Binary output Channel limiter mapping Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2 Channel x output source from Channel1 Channel 2 Channel 3 Doc ID 15251 Rev 4 STA339BW Mode ...

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... STA339BW 6.10 Tone control register (addr 0x11 TTC3 TTC2 0 1 6.10.1 Tone control Table 65. Tone control boost/cut as a function of BTC and TTC bits BTC[3:0]/TTC[3:0] 0000 0001 … 0111 0110 0111 1000 1001 … 1101 1110 1111 6.11 Dynamic control registers (addr 0x12 - 0x15) 6 ...

Page 52

... EATHx[6: recommended in anti-clipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of a FFX amplifier. Since gain can be added digitally within the STA339BW it is possible to exceed 0 dBfs or any other LxAT setting, when this occurs, the limiter, when active, automatically starts reducing the gain ...

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... STA339BW Figure 19. Basic limiter and volume flow diagram Table 66. Limiter attack rate as a function of LxA bits LxA[3:0] Attack Rate dB/ms 0000 3.1584 0001 2.7072 0010 2.2560 0011 1.8048 0100 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 1000 0.1504 1001 0.1123 1010 0.0902 1011 0 ...

Page 54

... LxRT[3:0] -∞ 0000 0001 -29 dB 0010 -20 dB 0011 -16 dB 0100 -14 dB 0101 -12 dB 0110 -10 dB 0111 -8 dB 1000 -7 dB 1001 -6 dB 1010 -5 dB 1011 -4 dB 1100 -3 dB 1101 -2 dB 1110 -1 dB 1111 -0 dB Doc ID 15251 Rev 4 STA339BW AC (dB relative to fs) ...

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... STA339BW Dynamic range compression mode Table 70. Limiter attack threshold as a function of LxAT bits (DRC- Mode) LxAT[3:0] DRC (dB relative to Volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 1000 -16 1001 -15 1010 -14 1011 -13 1100 -12 1101 -10 1110 -7 1111 -4 6.11.5 Limiter 1 Extended attack threshold (addr 0x32) ...

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... C1B21 C1B20 C1B19 C1B13 C1B12 C1B11 C1B5 C1B4 C1B3 Doc ID 15251 Rev 4 STA339BW EATH2[2] EATH2[1] EATH2[0] TBD TBD TBD ERTH2[2] ERTH2[1] ERTH2[0] TBD TBD TBD CFA2 CFA1 CFA0 ...

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... STA339BW 6.12.5 Coefficient b2 data register bits 23: C2B23 C2B22 0 0 6.12.6 Coefficient b2 data register bits 15 C2B15 C2B14 0 0 6.12.7 Coefficient b2 data register bits 7 C2B7 C2B6 0 0 6.12.8 Coefficient a1 data register bits 23: C1B23 C1B22 0 0 6.12.9 Coefficient a1 data register bits 15 C3B15 C3B14 0 0 6.12.10 Coefficient a1 data register bits 7:0 ...

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... D7 D6 Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA339BW via RAM. Access to this RAM is available to the user via an I register interface. A collection of I coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM ...

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... STA339BW For example, in case of different input sources (different sampling rates), the three different sets of coefficients can be downloaded once at the start up, and during the normal play it is possible to switch among the three RAM blocks allowing a faster operation, without any additional download from the microcontroller. ...

Page 60

... When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example 10, 20, 35 decimal), and the STA339BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data. 60/ register 0x16 ...

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... STA339BW 6.12.18 User-defined EQ The STA339BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0 ...

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... Register description 6.12.21 Over-current post-scale The STA339BW provides a simple mechanism for reacting to over-current detection in the power-block. When the ocwarn input is asserted, the over-current post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels. The default setting provides output attenuation when ocwarn is asserted. ...

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... STA339BW Table 72. RAM block for biquads, mixing, scaling and bass management (continued) Index (decimal) Index (hex) 54 0x36 55 0x37 56 0x38 57 0x39 58 0x3A 59 0x3B 60 0x3C 61 0x3D 62 0x3E 63 0x3F 6.13 Variable max power correction registers (addr 0x27 - 0x28 MPCC15 MPCC14 MPCC7 MPCC6 ...

Page 64

... TWARN fault condition Doc ID 15251 Rev FDRC11 FDRC10 FDRC9 FDRC3 FDRC2 FDRC1 OCFAULT OCWARN TFAULT Description STA339BW D0 FDRC8 0 D0 FDRC0 0 D0 TWARN ...

Page 65

... STA339BW 6.17 EQ coefficients and DRC configuration register (addr 0x31 XOB 0 0 Table 74. EQ RAM select SEL[1:0] 00/ Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in Table 75. Anti-clipping and DRC preset AMGC[3: 10/11 When AMGC[3: then the bits 1:0 are defined as given here in Table 76 ...

Page 66

... Register description 6.18.1 Dual-band DRC The STA339BW provides a dual-band DRC (B path, as depicted in 2 Figure 20. B DRC scheme The low-frequency information (LFE) is extracted from the left and right channels by removing the high frequencies with a programmable Biquad filter, so that, using the original signal, the difference signal can be computed ...

Page 67

... STA339BW A first-order filter is suggested to guarantee that for every ω filter obtained as difference (as shown in filter) frequency response, and the corresponding recombination after the DRC has low ripple. Second-order filters can be used as well, but in this case the filter shape must be carefully choosen to provide good low pass response and minimum ripple recombination. ...

Page 68

... Post-scale value is applied with +48-dB offset with respect to the coefficient RAM value Table 66 can be extended to provide dB/ms attack rate on Limiter1 attack rate is configured using Limiter1 attack rate is 8 dB/ms Limiter2 attack rate is configured using Limiter2 attack rate is 8 dB/ms Doc ID 15251 Rev 4 STA339BW Mode Mode Table 66 Mode Table 66 ...

Page 69

... STA339BW 6.18.5 Extended BIQUAD selector De-ephasis filter as well as bass and treble controls can be configured as user defined filters when equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1. Table 80. De-emphasis filter setup BQ5 0 1 Table 81. Bass filter setup BQ6 0 1 Table 82. ...

Page 70

... R_C1[21] R_C1[20] R_C1[19 R_C1[13] R_C1[12] R_C1[11 R_C1[5] R_C1[4] R_C1[ Doc ID 15251 Rev 4 STA339BW Mode Mode R_C0[18] R_C0[17] R_C0[16 R_C0[10] R_C0[9] R_C0[ R_C0[2] R_C0[1] R_C0[ ...

Page 71

... PLL without any resistive path. Concerning the component values, remember that the greater is the filter bandwidth, the less is the lock time but the higher is the PLL output jitter. below is the typical application diagram for STA339BW showing the power Doc ID 15251 Rev 4 Application ...

Page 72

... Doc ID 15251 Rev 4 STA339BW LEFT LEFT LEFT 470nF 470nF 470nF RIGHT RIGHT RIGHT 470nF 470nF 470nF ...

Page 73

... The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. Thus, the maximum estimated dissipated power for the STA339BW is Ω Ω, 8 Ω Figure 24. Double-layer PCB with 2 copper ground areas and 16 via holes ...

Page 74

... Package information 9 Package information Figure 26 shows the package outline and Figure 26. PowerSSO-36 slug down outline drawing 74/77 Table 85 gives the dimensions. Doc ID 15251 Rev 4 STA339BW ...

Page 75

... STA339BW Table 85. PowerSSO-36 slug down dimensions Symbol Min A 2. 0.18 c 0.23 D 10. 10. 0. 4.10 Y 4.90 In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...

Page 76

... Updated bits 4 and 5 in Doc ID 15251 Rev 4 Changes Chapter 2 on page interface setup in Section 3.6: Power Table 85: PowerSSO-36 slug down to “8 programmable 28-bit biquads” Table 6: Electrical specifications - digital section Table 7: Electrical specifications - power Section 6.1.5: Fault detect Table 73: Status register bits on page STA339BW 64. ...

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... STA339BW Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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