at42qt2160 ATMEL Corporation, at42qt2160 Datasheet

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at42qt2160

Manufacturer Part Number
at42qt2160
Description
Qslide?, 16-key Qmatrix? Sensor Ic
Manufacturer
ATMEL Corporation
Datasheet

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Features
1. Overview
The
(constructed from 2 keys up to 8 keys). There are three dedicated General Purpose
Input/Outputs (GPIOs) which can be used as inputs for mechanical switches etc. or as driven
outputs. There are eight shared General Purpose Outputs (GPOs) (X0...X7) which are driven
outputs only. There is PWM control for all GPIO/GPOs.
The QMatrix™ technology employs transverse charge-transfer sensing electrode
designs which can be made very compact and are easily wired. Charge is forced from
an emitting electrode into the overlying panel dielectric, and then collected on a
receiver electrode. This directs the charge into a sampling capacitor which is then
converted directly to digital form, without the use of amplifiers.
The keys are configured in a matrix format that minimizes the number of required scan
lines and device pins. The key electrodes can be designed into a conventional Printed
Circuit Board (PCB) or Flexible Printed Circuit Board (FPCB) as a copper pattern, or
as printed conductive ink on plastic film.
Number of keys: up to 16 keys, and one slider (constructed from 2 to 8 keys)
Number of I/O lines: 11 (3 dedicated - configurable for input or output, 8 shared -
output only), PWM control for LED driving
Technology: patented spread-spectrum charge-transfer (transverse mode)
Key outline sizes: 6 mm x 6 mm or larger (panel thickness dependent); widely different
sizes and shapes possible
Key spacings: 8 mm or wider, center to center (panel thickness dependent)
Slider design: 2 to 8 keys placed in sequence, same design as keys
Electrode design: two-part electrode shapes (drive-receive); wide variety of possible
layouts
PCB layers required: one layer (with jumpers), two layers (no jumpers)
Electrode materials: PCB, FPCB, silver or carbon on film, ITO on film
Panel materials: plastic, glass, composites, painted surfaces (low particle density
metallic paints possible)
Adjacent metal: compatible with grounded metal immediately next to keys
Panel thickness: up to 3 mm glass, 2.5 mm plastic (key size dependent)
Key sensitivity: individually settable via simple commands over I
interface
Interface: I
Moisture tolerance: best in class
Power: 1.8 V to 5.5 V
Package: 28-pin 4 x 4 mm MLF RoHS compliant
Signal processing: self-calibration, auto drift compensation, noise filtering, Adjacent
Key Suppression
Applications: laptop, mobile, consumer appliances, PC peripheral etc.
Patents: AKS™ (patented Adjacent Key Suppression™) technology
QMatrix™ (patented charge-transfer method)
QSlide™ (patented charge-transfer method) (patent-pending QSlide sensing
configuration)
This datasheet is applicable to revision 4R0 chips only
AT42QT2160-MMU
2
C-compatible slave mode (100kHz)
TM
technology
(
QT2160
) is designed for use with up to 16 keys and a slider
2
C-compatible
QSlide™, 16-key
QMatrix™
Sensor IC
AT42QT2160
9502A–AT42–07/08

Related parts for at42qt2160

at42qt2160 Summary of contents

Page 1

... The key electrodes can be designed into a conventional Printed Circuit Board (PCB) or Flexible Printed Circuit Board (FPCB copper pattern printed conductive ink on plastic film. 2 C-compatible ) is designed for use with keys and a slider QSlide™, 16-key QMatrix™ Sensor IC AT42QT2160 9502A–AT42–07/08 ...

Page 2

... Pinout and Pin Listing Description 2.1 Pinout Description GPIO2 GPIO3 CHANGE 2.2 Pin Listing Description Table 2-1.Pin Listing Pin AT42QT2160 VDD QT2160 4 VSS Function I/O GPIO2 I/O GPIO3 I/O Vdd ...

Page 3

... GPIO1 I/O 3-1). The QT2160 allows a wide range of key sizes and shapes to be mixed together -compatible interface to allow key data to be extracted and to permit I C AT42QT2160 Comments X matrix drive line / shared GPO X4 X matrix drive line / shared GPO X5 Power Power Supply ground ...

Page 4

... The burst length directly impacts key gain; each key can have a unique burst length in order to allow tailoring of key sensitivity on a key-by-key basis. AT42QT2160 4 Field Flow Between X and Y Elements ...

Page 5

... Section 4.4. shows a defective waveform similar to that of Figure 4-3. Note that the bottom edge of the bottom trace is AT42QT2160 Figure 4-8 on page 15. The value of these Figure 4-1. Saturation begins to occur when the Figure 4-1, but in this case the ...

Page 6

... Unlike other QT circuits, the Cs capacitor values on QT2160 devices have no effect on conversion gain. However, they do affect conversion time. Unused Y lines should be left open. Figure 4-1. Figure 4-2. Figure 4-3. AT42QT2160 6 VCs – Nonlinear During Burst (Burst too long too small, or X-Y transcapacitance too large) X Drive YnB VCs – ...

Page 7

... Drive Pulse Roll-off and Dwell Time X drive Dwell time Y gate The Dwell time is a minimum of ~250ns - see (Figure 4-8 on page AT42QT2160 Lost charge due to inadequate settling before end of dwell time Section 4.7 15). 7 ...

Page 8

... The internal pattern can be interdigitated as shown in For small, dense keypads, electrodes such as shown in the lower half of Where the panels are thin (under 2 mm thick) the electrode density can be quite high. AT42QT2160 8 7). Increasing Rx values will cause the leading edge of the X pulses to increasingly roll (Figure 4-5) ...

Page 9

... Smaller dimensions will also work but will give less signal strength doubt, make the pattern coarser. The lower figure shows a simpler structure used for compact key layouts, for example for mobile phones. A layout with a common X drive and two receive electrodes is depicted AT42QT2160 ...

Page 10

... SNR performance of the device. Such signals should be routed away from the Y lines, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). AT42QT2160 10 For normal operation all keys in the slider should be placed in the same AKS group. ...

Page 11

... Load shifts on the output of the LDO can cause Vdd to fluctuate enough to cause false detection or sensitivity shifts. 9502A–AT42–07/08 Position of Tracks Example of g ood tracking for the Vdd range and short-term power supply fluctuations. If the AT42QT2160 Example of bad tracking 11 ...

Page 12

... The pin is active low, and a low pulse lasting at least 10µs must be applied to this pin to cause a reset external hardware reset is not used, the reset pin may be connected to Vdd. AT42QT2160 12 by the user ...

Page 13

... GPIO inputs, then the QT2160 will trigger the CHANGE line if a change in status (either positive or negative going edge) of the respective GPIO is detected, in SLEEP mode. 9502A–AT42–07/08 Section 4.2 on page 5. Section 4.2 on page AT42QT2160 5) is used for conserving power when there are -compatible bus, a ...

Page 14

... The dedicated GPIOs have a Wake option, that if enabled will enable dedicated GPIOs set as inputs read in SLEEP mode. Note that shared GPOs (X0...X7) are driven by the burst pulses during acquisition bursts, if the corresponding X line is used in the keys/slider. A low pass filter can be inserted to eliminate these burst pulses, as shown in AT42QT2160 14 Figure 4-9 on page 16. 9502A–AT42–07/08 ...

Page 15

... Cs capacitors (Cs0...Cs1) 7: Sample resistors (Rs0...Rs1) 7: Matrix resistors (Rx0...Rx7, Ry0...Ry1) 11: Voltage levels 22: SDA, SCL pull-up resistors (Rp) 5: CHANGE resistor (Rchg -compatible addresses I C AT42QT2160 Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 General purpose inputs/outputs Ry0 ...

Page 16

... Figure 4-9. AT42QT2160 16 Inputs/Outputs 9502A–AT42–07/08 ...

Page 17

... -compatible Interface Bus I C Device 1 Device 2 Device 3 SDA SCL 2 -compatible Bus Specifications I C AT42QT2160 2 -compatible bus as shown in Figure -compatible I C Vdd Device Unit 7-bit 100 kHz 4 µs minimum 4 µs minimum 4.7 µ ...

Page 18

... SDA low in the ninth SCL (ACK) cycle. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. The most significant bit of the address byte is transmitted first. The address sent by the host must be consistent with that selected with the option jumpers. AT42QT2160 18 Data Transfer SDA ...

Page 19

... Note: Each write or read cycle must end with a STOP condition. The QT2160 may not respond correctly if a cycle is terminated by a new START condition. 9502A–AT42–07/08 Address Packet Format Addr MSB SDA SCL 1 2 START 2 -compatible unit reset AT42QT2160 Addr LSB R/W ACK ...

Page 20

... Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master Figure 5-6. SDA SCL START AT42QT2160 20 shows a typical data transmission. Note that several data bytes can be transmitted Data Packet Format Data MSB 1 2 SLA+R/W Packet Transmission Addr MSB Addr LSB R/W ACK ...

Page 21

... I2CA0 and I2CA1 -compatible Addresses I C I2CA1 Host to Device S SLA+W A MemAddress AT42QT2160 I2CA0 Device to Host A Data A Start condition Slave address plus write bit Acknowledge bit Target memory address within device Data to be written Stop condition (Table 6-1) ...

Page 22

... If the host cannot make use of the CHANGE pin, the poll rate should be no faster than once per matrix scan (see will slow down the chip operation. The CHANGE pin requires a pull-up resistor, with a typical value of ~100kΩ. AT42QT2160 22 Host to Device S SLA+W ...

Page 23

... Drift Hold Time/AWAKE 20 Slider Control 21 Slider Options 22...37 Key Key Control 38...53 Key Neg Threshold 54...69 Key Burst Length 70 GPIO/GPO Drive 1 AT42QT2160 shows the address map of QT2160. Use Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write ...

Page 24

... Address 1: Code Version Table 7-3. Address 1 There is an 8-bit major and minor version of firmware code revision. The top nibble of the firmware version register contains the major version (e.g. 4.0) and the bottom nibble contains the minor version (e.g. 4.0). AT42QT2160 24 Memory Map (continued) Address 71 GPIO/GPO Drive 2 72 ...

Page 25

... General Status CYCLE OVER RESET 0 RUN 2 -compatible lines, for clock stretching or other purposes, will I C 35). Key Status and Numbering k15 k14 k13 AT42QT2160 k12 k11 k10 k9 b0 SDET b0 k0 ...

Page 26

... Table 7-8. Address 7 This is an 8-bit sub-revision number that follows the code version (e.g. 4.0.0). 7.9 Address 10: Calibrate Table 7-9. Address 10 Writing any nonzero value into this address will trigger the QT2160 to start a recalibration on all enabled keys. AT42QT2160 26 Slider Touch Position GPIO Read ...

Page 27

... The BREP value can range between 1...63 repetitions. Do not set to 0 because it is not valid. Default value:1 (one measurement burst) 9502A–AT42–07/08 Reset Mode Section 4.17 on page Table 10-1 on page 45 Burst Repetition AT42QT2160 RESET LP_MODE 13). for typical power consumptions ...

Page 28

... PDRIFT Setup parameters. This is a global configuration. Specifically, drift compensation should be set to compensate faster for increasing signals than for decreasing signals. Decreasing signals should not be compensated quickly, since an approaching finger could be compensated for partially or entirely before even touching the touchpad (NDRIFT). AT42QT2160 28 Neg/Pos Drift Compensation b7 b6 ...

Page 29

... If an object unintentionally contacts a key resulting in a detection for a prolonged interval it is usually desirable to recalibrate the key in order to restore its function, perhaps after a time delay of some seconds. 9502A–AT42–07/08 Detect Integrator Negative Recal Delay AT42QT2160 NDIL NRD ...

Page 30

... DHT/AWAKE can be configured to a value of between 0.32s and 40.8s, in increments of 0.16s. Values of 0 and 1 are invalid and should not be used. Note recommended having a DHT/AWAKE of at least two seconds to prevent unintended key sensitivity drifts and the slider being unresponsive in longer LP modes. DHT/AWAKE Default: 25 (4s) AT42QT2160 30 Drift Hold Time/Awake Timeout b7 b6 ...

Page 31

... Slider Control HYST Slider Options Resolution Value Resolution 0 8 bits (0-255 bits (0-127 bits (0-63 bits (0-31) AT42QT2160 NUM_KEYS RESOLUTION Value Resolution 4 4 bits (0-15 bits (0- bits (0- ...

Page 32

... Address 54...69: Burst Length Table 7-22. Address 54...69 The QT2160 uses a fixed number of pulses which are executed in burst mode. This number is set in groups of four. Therefore, the value send to the QT2160 is multiplied by four to get the actual number of burst pulses. AT42QT2160 32 Key Control ...

Page 33

... Sets the direction of the GPIOs driven outputs floating inputs. If set as inputs, the GPIO will only be read every 16ms (fixed cycle time). 9502A–AT42–07/08 GPIO/GPO Drive GPIO3 GPIO Direction GPIO3 AT42QT2160 GPIO2 GPIO1 GPIO2 GPIO1 ...

Page 34

... This sets the Duty Cycle of the PWM enabled pins. Valid values are between 0 to 255. A value of 0...10 will be 100 percent duty cycle (always on), and a value of 250...255 will be 0 percent duty cycle (always off). Default: 0 (100 percent duty cycle) AT42QT2160 34 GPIO/GPO PWM b7 ...

Page 35

... GPIO3 Common Change Keys k15 k14 k13 Signal and References Key # Use 0 Signal LSB 0 Signal MSB 1 Signal LSB 1 Signal MSB 2...15 AT42QT2160 GPIO2 GPIO1 k12 k11 k10 k9 Address Key # 132 0 Reference LSB ...

Page 36

... Drift Hold 19 1 Time/Awake Timeout 20 1 Slider Control 21 1 Slider Options 22...37 16 Key Control 38...53 16 Neg threshold 54...69 16 Burst Length AT42QT2160 36 2 -compatible interface. The setups block is memory mapped I C Valid Key Symbol Range Bits Scope LP_MODE 0 - 255 8 16 BREP 1... NDRIFT 0 ...

Page 37

... GPIO3 0... GPIO2 0... GPIO1 0... AT42QT2160 Default Value Description GPO driven low 1: GPO driven high GPIO set to output GPIO driven low 0 1: GPIO driven high GPIO is floating input ...

Page 38

... Table 8-1. Setups Table (continued) Address Bytes Parameter 74 1 GPO PWM GPIO PWM PWM Level 77 1 GPIO Wake Common 78...79 2 Change Keys AT42QT2160 38 Valid Key Symbol Range Bits Scope X7 0... 0... 0... 0... 0... 0...1 ...

Page 39

... Section 6.1). The next byte is the address of the location into which the writing 2 -compatible bus. A new write cycle will involve sending another address I C 6.1). Bytes can then be read starting at the location pointed to by the address AT42QT2160 Section 9.3). Now read 2 -compatible address ...

Page 40

... AKS technology will lock out anything else in the same AKS group. Similarly, a key in the same AKS group as the slider can lock out the slider as a whole object. Note: for normal operation all keys in the slider should be placed in the same AKS group. AT42QT2160 40 5) will also help. 9502A–AT42–07/08 ...

Page 41

... Input - read in LP and Sleep modes CHANGE event possible in both modes shows a typical example of communicating with the QT2160. AT42QT2160 Shared GPO Function Output - Gnd Output - Vdd Output - PWM Always output Always output Output - Gnd Output - Vdd Output - PWM 41 ...

Page 42

... Figure 9-1. AT42QT2160 42 Typical Initialization and Usage Reset/Power Up CHANGE pin active (low)? Send setup parameters to set up QT2160 Send Calibrate command Read all status bytes (Address 2...6) to restore CHANGE pin to inactive (high) CHANGE pin active (low)? Read required Status bytes and other status bytes that changed, to restore CHANGE pin to inactive (high) ...

Page 43

... Cx transverse load capacitance per key Note: *Applicable to QT2160 on a typical setup, with Burst Repetition (BREP The effects of supply ripple and noise on performance is more prominent the nearer the burst center frequency. 9502A–AT42–07/08 AT42QT2160 -0.5 to +6V ±10 mA infinite infinite -0.6V to (Vdd + 0.6) Volts ...

Page 44

... Input leakage current Ar Acquisition resolution Internal RST Rrst pull-up resistor 10.4 Timing Specifications Parameter Description T Burst duration BS Fc Burst center frequency Fm Burst modulation, percentage T Dwell time DW T Pulse width PW AT42QT2160 44 Min Typ Max 476 955 1127 <1.5 <2 <3 0.2Vdd 0.6Vdd 0.2 4 Min Typ Max 40 80 ...

Page 45

... SLEEP 128 ms LP 256 ms LP 512 ms LP 1024 ms 9502A–AT42–07/08 Idd (µA) at Vdd = 1.8V 3.3V <1.5 <2 476 955 311 609 229 436 188 350 167 306 157 285 152 274 AT42QT2160 5V <3 1,127 770 592 502 458 435 424 45 ...

Page 46

... TOP VIEW 0.20 b BOTTOM VIEW The terminal # Laser-marked Feature. Note: TITLE 2325 Orchard Parkway San Jose, CA 95131 R AT42QT2160 28M1, 28-pad 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 mm Exposed Pad, Micro Lead Frame Package (MLF) C SIDE VIEW ...

Page 47

... Part number; 2160 AT42QT AT Peak Body Temperature MSL3 260 AT42QT2160 Part number; AT42QT2160-MMU Chip Assembly Lotcode (for traceability) Program week code number 1-52 where 2... then using the underscore A = 27... Description 28-pin 4 x 4mm MLF RoHS compliant IC Specifications ...

Page 48

... Revision History Revision No. Revision A – July 2008 AT42QT2160 48 History • Initial Release 9502A–AT42–07/08 ...

Page 49

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel QMatrix™, and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...

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