adt7476a Analog Devices, Inc., adt7476a Datasheet - Page 56

• Manufacturer Part Number: adt7476a
• Description: Dbcool Remote Thermal Controller And Voltage Monitor
• Manufacturer: Analog Devices, Inc.

ADT7476A
Table 26. Register 0x40—Configuration Register 1 (Power-On Default = 0x04)
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
1
2
Table 27. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00)
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after lock bit is set.
When monitoring (STRT) is disabled, PWM outputs always go to 100% for thermal protection.
Name
2.5 V/
THERM
5 V
R1T
LT
R2T
OOL
V
V
Name
LOCK
RDY
FSPD
FSPDIS
TODIS
STRT
Vx1
Reserved
CCP
CC
1,2
R/W
Read/Write
Write once
Read-only
Read/Write
Read/Write
Read/Write
Read/Write
N/A
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Description
2.5 V = 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided. If Pin 22 is configured as THERM, this bit is
asserted when the timer limit has been exceeded.
V
status register only if the error condition has subsided.
V
status register only if the error condition has subsided.
A 1 indicates that the 5 V high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided.
R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
OOL = 1 indicates that an out-of-limit event has been latched in Interrupt Status Register 2. This bit is a
logical OR of all status bits in Interrupt Status Register 2. Software can test this bit in isolation to
determine whether any of the voltage, temperature, or fan speed readings represented by Interrupt
Status Register 2 are out-of-limit, which eliminates the need to read Interrupt Status Register 2 during
every interrupt or polling cycle.
Description
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control is based on the default power-up limit settings.
Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the
default settings are enabled. This bit does not become locked once Bit 1 (LOCK bit) has been set.
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become
read-only and cannot be modified until the ADT7476A is powered down and powered up again. This
prevents rogue programs such as viruses from modifying critical system limit settings. (Lockable.)
This bit is set to 1 by the ADT7476A to indicate that the device is fully powered-up and ready to begin
system monitoring.
When set to 1, this bit runs all fans at max speed as programmed in the max PWM current duty cycle
registers (0x30 to 0x32). Power-on default = 0. This bit is not locked at any time.
BIOS should set this bit to a 1 when the ADT7476A is configured to measure current from an ADOPT®
VRM controller and to measure the CPU’s core voltage. This bit allows monitoring software to display
CPU watts usage. (Lockable.)
Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan
spin-up timeout selected.
When this bit is set to 1, the SMBus timeout feature is enabled.
In this state, if at any point during an SMBus transaction involving the ADT7476A activity ceases for
more than 35 ms, the ADT7476A assumes the bus is locked and releases the bus. This allows the
ADT7476A to be used with SMBus controllers that cannot handle SMBus timeouts. (Lockable.)
Reserved. Do not write to this bit.
CCP
CC
= 1 indicates that the V
= 1 indicates that the V
CC
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CCP
high or low limit has been exceeded. This bit is cleared on a read of the
high or low limit has been exceeded. This bit is cleared on a read of the