fin24amlx Fairchild Semiconductor, fin24amlx Datasheet
fin24amlx
Related parts for fin24amlx
fin24amlx Summary of contents
Page 1
... FIN24AGFX BGA042A Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, (Preliminary) 3.5mm Wide FIN24AMLX MLP040A Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square Pb-Free package per JEDEC J-STD-020B. BGX and MLP packages available in Tape and Reel only. ...
Page 2
Functional Block Diagram Connection Diagram www.fairchildsemi.com Terminal Assignments for MLP (Top View) 2 Preliminary ...
Page 3
Terminal Description Number Terminal Name I/O Type of Terminals DP[1:20] I/O 20 DP[21:22 DP[23:24 CKREF IN 1 STROBE IN 1 CKP OUT 1 DSO / DSI DIFF-I/O 2 DSO / DSI CKSI , SKSI DIFF-IN 2 ...
Page 4
TABLE 1. Control Logic Circuitry Mode S2 S1 DIRI Description Number Power-Down Mode 24-Bit Serializer 2MHz to 5MHz CKREF 24-Bit Deserializer 24-Bit Serializer 5MHz to ...
Page 5
Serializer Operation Mode FIGURE 1. Serializer Timing Diagram (CKREF equals STROBE) FIGURE 2. Serializer Timing Diagram (CKREF does not equal STROBE) FIGURE 3. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) (Continued) 5 Preliminary www.fairchildsemi.com ...
Page 6
Deserializer Operation Mode The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI clock signal pair. The following two sections describe the operation of the deserializer under two distinct ...
Page 7
Embedded Word Clock Operation The FIN24A sends and receives serial data source syn- chronously with a bit clock. The bit clock has been modified to create a word boundary at the end of each data word. The word boundary has ...
Page 8
PLL Circuitry The CKREF input signal is used to provide a reference to the PLL. The PLL will generate internal timing signals capable of transferring data at 26 times the incoming CKREF signal. The output of the PLL is a ...
Page 9
Application Mode Diagrams FIGURE 9. Unidirectional Serializer and Deserializer FIGURE 10. Multiple Units, Unidirectional Signals in Each Direction Figure 10 shows a half duplex connectivity diagram. This connectivity allows for two unidirectional data streams to be sent across a single ...
Page 10
Absolute Maximum Ratings Supply Voltage ( ALL Input/Output Voltage LVDS Output Short Circuit Duration Storage Temperature Range (T ) STG Maximum Junction Temperature ( Lead Temperature ( (Soldering, 4 seconds) ESD Rating Human Body ...
Page 11
DC Electrical Characteristics Symbol Parameter I Input Current Note 3: Typical Values are given for V 2.5V and T DD current flowing out of pins. Voltage are referenced to GROUND unless otherwise specified (except Note ...
Page 12
AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Serializer Electrical Characteristics t CKREF Clock Period TCP (2 MHz - 30 MHz) f CKREF Frequency Relative REF to Strobe Frequency t CKREF Clock High ...
Page 13
Control Logic Timing Controls Symbol Parameter t , Propagation Delay PHL_DIR DIRI LOW-to-HIGH or HIGH-to-LOW t DIRI-to-DIRO PLH_DIR t , Propagation Delay PLZ DIRI LOW-to-HIGH t DIRI-to-DP PHZ t , Propagation Delay PZL DIRI HIGH-to-LOW t DIRI-to-DP PZH t , ...
Page 14
AC Loading and Waveforms FIGURE 11. Differential LpLVDS Output DC Test Circuit Note: The Worst Case test pattern produces a maximum toggling of internal digital circuits, LpLVDS I/O and LVCMOS I/O with the PLL operating at the ref- erence frequency ...
Page 15
AC Loading and Waveforms Setup: MODE0 “0” or “1”, MODE1 “1”, SER/DES “1” FIGURE 16. Serial Setup and Hold Time Setup: EN_DES “1”, CKSI and DSI are valid signals FIGURE 18. Deserializer Data Valid Window Time and Clock Output Parameters ...
Page 16
AC Loading and Waveforms FIGURE 22. Differential Input Setup and Hold Times Note: CKREF Signal can be stopped either HIGH or LOW FIGURE 24. PLL Loss of Clock Disable Time Note: CKREF must be active and PLL must be stable ...
Page 17
Tape and Reel Specification TAPE FORMAT for USS-BGA Dimensions are in millimeters Package 0.10 0.10 0.05 min 3.5 x 4.5 TBD TBD 1.55 1.5 Note: A0, B0, and K0 dimensions are determined with ...
Page 18
Tape and Reel Specification TAPE FORMAT for MLP Package Tape Designator Section Leader (Start End) MLX Carrier Trailer (Hub End) MLP Embossed Tape Dimension www.fairchildsemi.com (Continued) Number Cavity Cavities Status 125 (typ) Empty 3000 Filled 75 (typ) Empty 18 Preliminary ...
Page 19
Physical Dimensions inches (millimeters) unless otherwise noted Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide Package Number BGA042A 19 Preliminary www.fairchildsemi.com ...
Page 20
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...