lm2507gr National Semiconductor Corporation, lm2507gr Datasheet
lm2507gr
Related parts for lm2507gr
lm2507gr Summary of contents
Page 1
... The LM2507 implements the physical layer of the MPL Level 0 Standard (MPL-0) and a 150 µ Typical Application Diagram - CPU Mode © 2006 National Semiconductor Corporation Features n CPU Display Interface support up to 800 x 300 n Dual displays supported – CS1 n MPL-Level 0 Physical Layer using two data and one ...
Page 2
Pin Descriptions — CPU Pin Name I/O, Type No. of Pins MPL SERIAL BUS PINS MD[1:0] 2 IO, MPL MC 1 IO, MPL V Ground SSA CONFIGURATION/PARALLEL BUS PINS CPU 1 I, LVCMOS M/ LVCMOS ...
Page 3
... DAP 1 Note Input Output Input/Output. Do not float input pins. Ordering Information NSID LM2507GR LM2507SQ (Continued) CPU Master (MST) Power Supply Pin for the MST PLL and MPL Interface. 1.74V to 2.0V Ground Pin for the MPL Interface, and analog circuitry. Power Supply Pin for the digital core. 1.74V to 2.0V Ground Pin for the digital core ...
Page 4
Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V ) DDA Supply Voltage ( Supply Voltage (V ) DDIO LVCMOS Input/Output Voltage MPL ...
Page 5
Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3) Symbol Parameter SUPPLY CURRENT I Supply Current — Disable DDZ T = 25˚C A Power Down Modes Switching Characteristics Over recommended operating supply and temperature ...
Page 6
Recommended Input Timing Requirements Note 5: Total Supply Current Conditions: CPU Mode, worse case data pattern, 19.2MHz CLK, DES C = 3.0V and 2.0V. DDA DDcore Note 6: Applies and RD * outputs ...
Page 7
Functional Description FIGURE 4. Dual Link Timing (WRITE) FIGURE 5. Dual Link Timing (READ) Name MC State OFF (O) 0 IDLE (I) A ACTIVE(A) Data Out A WRITE Data In A READ LINK-UP (LU) H Notes on MC/MD Line State: ...
Page 8
Functional Description OFF PHASE In the OFF phase, both Master and Slave MPL transmitters are turned off with zero current flowing on the MC and MDn lines. Figure 7 shows the transition of the MPL bus into the OFF phase. ...
Page 9
Functional Description READ TRANSACTION The READ transaction is fixed in length. It consists of four sections. In the first section the Master sends a READ Command to the slave. This command is sent in a single MC cycle (2 edges) ...
Page 10
Functional Description To account for the latency through the MPL link, a dual READ operation is required by the host. The first read re- turns invalid data (all Low), which the host ignores. Once data has returned to the Master, ...
Page 11
Functional Description TABLE 2. WRITE — i80 CPU Interface Parameters No. T1 MasterIN Data Setup before Write* High T2 MasterIN Data Hold after Write* High T3 MasterIN Write* Cycle Rate T4 Master Master Latency T5 Slave Slave Latency T6 SlaveOUT ...
Page 12
www.national.com 12 ...
Page 13
Functional Description TABLE 3. READ — i80 CPU Interface Parameters No. T1 MasterIN Set Up Time (A/D, RD*) and Data On Time T2 MasterIN Hold Time (A/D, RD*) and Data Off Time T3 Master Master Latency T4 Slave Slave Latency ...
Page 14
Functional Description FIGURE 14. Two WRITE Timing – Master IN vs. Slave OUT LM2507 Features and Operation POWER SUPPLIES The V and V (MPL and PLL) must be connected to DDcore DDA the same potential between 1.74V and 2.0V. V ...
Page 15
LM2507 Features and Operation (Continued) On both the Master and the Slave, the PD* pin resets the logic. The PD* pins should be held low until the power supply has ramped up and is stable and within specifi- cations. Power ...
Page 16
Application Information MPL SWAP FEATURE The LM2507 provides a swap function of MPL MD lines depending upon the state of the M/S* pin. This facilitates a FIGURE 16. MPL Interface Layout and Flow Through Pinout www.national.com straight through MPL interface ...
Page 17
Application Information Power and Ground - Bumped Package Power and ground bump assignments are shown in Figure 17. The nine center balls must be connected ground on the FIGURE 17. LM2507 PWR (V FLEX CIRCUIT RECOMMENDATIONS The three MPL lines ...
Page 18
Application Information FIGURE 18. MPL Interface Layout – microArray to LLP Package DISPLAY APPLICATION The LM2507 chipset is intended for interfacing between a host (processor) and a Display. It supports a 16 8-bit i80 CPU style interfaces and ...
Page 19
Connection Diagram microArray Package Master (CPU) Pinout MST CPU B AD INTR MF0 (RD ) MF1 ( DDIO SSIO Slave CPU Pinout SLV ...
Page 20
Connection Diagram - LLP Package Pin # Master 1 M/S* 2 CSL DDA 4 MD1 5 V SSA MD0 8 Mode 9 CPU 10 INTR A/D 13 MF1 ( ...
Page 21
... Physical Dimensions inches (millimeters) unless otherwise noted 49L MicroArray, 0.5mm pitch Order Number LM2507GR NS Package Number GRA49A 40L LLP, 0.4mm pitch Order Number LM2507SQ NS Package Number SQF40A 21 www.national.com ...
Page 22
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information ...