lm2502sm National Semiconductor Corporation, lm2502sm Datasheet
lm2502sm
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lm2502sm Summary of contents
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... UFBGA and LLP packages. Typical Application Diagram Ordering Information NSID 49 Lead UFBGA style, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch LM2502SM 1000 std reel, LM2502SMX 4500 reel LM2502SQ 40 Lead LLP style, 5.0 X 5.0 X 0.8 mm, 0.4 mm pitch 1000 std reel, LM2502SQX 4500 reel © 2005 National Semiconductor Corporation Features > ...
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UFBGA Connection Diagram Ball # Master Note: Three pins are different between Master and Slave ...
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LLP Connection Diagram Pin # Master SSIO 6 V DDIO D10 10 D11 11 D13 12 D14 13 D12 14 D15 15 V SSIO 16 ...
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Pin Descriptions No. Pin Name I/O, Type of Pins MPL SERIAL BUS PINS MD[1:0] 2 IO, MPL MC 1 IO, MPL V Ground SSA CONFIGURATION/PARALLEL BUS PINS M/ LVCMOS PD LVCMOS MF0 1 IO ...
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Pin Descriptions (Continued) No. Pin Name I/O, Type of Pins POWER/GROUND PINS V 1 Power DDA V 1 Ground SSA V 1 Power DDcore V 1 Ground SScore V 2 Power DDIO V 2 Ground SSIO Ground ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V ) DDA Supply Voltage ( Supply Voltage (V ) DDIO LVCMOS Input/Output Voltage MPL ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3) Symbol Parameter SUPPLY CURRENT I Total Supply DD Current — Enabled Conditions 76.8 MHz 1010-0101 pattern (worse case toggle, rail-to-rail levels), ...
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Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter POWER UP TIMING(Note 5) MPL POWER OFF TIMING t Disable Time to Power PAZ Down Recommended Input Timing Requirements Over recommended operating supply and ...
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Functional Description BUS OVERVIEW The LM2502 is a dual link Transceiver configurable part that supports a 16-bit CPU (m68 or i80) style interface. The MPL physical layer is purpose-built for an extremely low power and low EMI data transmission while ...
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Functional Description SERIAL BUS PHASES There are four bus phases on the MPL serial bus. These are determined by the state of the MC and MD lines. The MPL bus phases are shown in Table 3 . Name MC State ...
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Functional Description OFF PHASE In the OFF phase, both Master and Slave MPL transmitters are turned off with zero current flowing on the MC and MD lines. Figure 7 shows the transition of the MPL bus into the OFF phase. ...
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Functional Description WRITE TRANSACTION The WRITE transaction consists of two MC edges of control information followed edges of write data. Since WRITE transactions transfer information on both edges takes 5 MC cycles to complete ...
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Functional Description fourth section the MD lines are again turned around, such that the Master becomes the transmitter and the Slave be- comes the receiver. The Slave drives the MD lines Low for 1 bit width and then turns off. ...
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Functional Description FIGURE 12. Back-to-Back WRITE Operations — m68 Mode Figure 12 illustrates a m68 mode WRITE operation to the main display (CS1*) followed by a WRITE operation to the sub display (CS2*). This example shows the maximum op- www.national.com ...
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Functional Description CPU MODE — WRITE — m68 (Continued) FIGURE 13. WRITE — MOT 6800 µP Interface 15 20093310 www.national.com ...
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Functional Description TABLE 5. WRITE — MOT 6800 µP Interface Parameters No. T1 MasterIN Data Setup Time before ChipSelect* Low-High (or E High-Low) T2 MasterIN Data Hold after ChipSelect* Low-High (or E High-Low) T3 MasterIN ChipSelect* Recovery Time, (Note 5) ...
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Functional Description CPU MODE — READ — m68 TABLE 6. READ — 6800 µP Interface Parameters No. T1 MasterIN Set Up Time (A/D, R/W T2 MasterIN Hold Time (A/D, R/W T3 Master Master Latency T4 Slave Slave Latency T5 Slave ...
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Functional Description TABLE 6. READ — 6800 µP Interface Parameters (Continued) No. T15 MasterOUT Recovery Time T16 MasterOUT INTR Response, (Note 5) For the MOT CPU 68xx mode, the Master accepts data on the CS* Low-to-High transition or the E ...
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Functional Description No. T1 MasterIN Set Up Time (A/ MasterIN Hold Time (A/ Master Master Latency T4 Slave Slave Latency T5 Slave Read* Delay T6 Slave Read Low Pulse Width T7 Slave Data Set Up Time ...
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LM2502 Features and Operation (Continued) between 3 and 25 MHz. See Table 10 below, Multiplier/ Divisor times CLK rate must also be less than 76.8 MHz. The 76.8 MHz limitation is based on the semiconductor process used on this implementation ...
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Application Information MPL SWAP FEATURE The LM2502 provides a swap function of MPL MD lines depending upon the state of the M/S* pin. This facilitates a straight through MPL interface design eliminating the needs for via and crossovers as shown ...
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Application Information FIGURE 18. LM2502 UFBGA Package PWR (V DISPLAY APPLICATION The LM2502 chipset is intended for Interface between a host (processor) and a Display. It supports 8-bit CPU style interface and can be configured for i80 ...
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Application Information RGB565 APPLICATION The LM2502 chipset may also be configured for a RGB565 application. This is also known as a "buffer-less" or "dumb" display application. In this configuration 16 color bits (R[4:0], G[5:0], B[4:0]), Pixel Clock (PCLK) and two ...
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Application Information Figure 21 shows the typical timing of the RGB application. The 6X PLL setting (PLLCON[2:0] = 010’b) is selected. The PCLK is applied to both the WR* and CLK inputs on the Master. The rising edge on the ...
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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 49 Lead UFBGA, 0.5mm pitch Order Number LM2502SM NS Package Number SLH49A 40 Lead LLP, 0.4mm pitch Order Number LM2502SQ NS Package Number SQF40A 26 ...
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information ...