lm2512 National Semiconductor Corporation, lm2512 Datasheet
lm2512
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lm2512 Summary of contents
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... Serializer with Dithering and Look Up Table Option — — NOT RECOMMENDED FOR NEW DESIGN - See LM2512A General Description The LM2512 is a MPL Serializer (SER) that performs a 24-bit to 18-bit Dither operation and serialization of the video signals to Mobile Pixel link (MPL) levels on only active signals. ...
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... Ordering Information NSID Package Type LM2512SM 49L UFBGA, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch LM2512SN 40L LLP, 6.0 X 6.0 X 0.4 mm, 0.5 mm pitch www.national.com 2 Package ID SLH49A SNA40A ...
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Pin Descriptions No. Pin Name of Pins MPL SERIAL BUS PINS MD[2: SPI INTERFACE and CONFIGURATION PINS SPI_CSX 1 SPI_SCL 1 SPI_SDA/HS 1 PD* 1 RES1 VIDEO INTERFACE PINS PCLK 1 R[7:0] ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V ) DDA Supply Voltage ( Supply Voltage (V ) DDIO LVCMOS Input/Output Voltage MPL ...
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Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter PARALLEL BUS TIMING t Set Up Time SET t Hold Time HOLD SERIAL BUS TIMING t Serial Data Valid before Clock DVBC Edge t ...
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Recommended Input Timing Requirements (PCLK and SPI) Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter PIXEL CLOCK (PCLK) f Pixel Clock Frequency PCLK PCLK Pixel Clock Duty Cycle DC t Transition Time T t ...
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Timing Diagrams FIGURE 1. Input Timing for RGB Interface FIGURE 2. Serial Data Valid FIGURE 3. Stop PClock Power Down FIGURE 4. Stop PClock Power Up 7 20172826 20172816 20172829 20172830 www.national.com ...
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... Functional Description The LM2512 is a Mobile Pixel Link (MPL) Serializer that se- rializes a 24-bit RGB plus three control signals (VS, HS, and DE) to two or three MPL MD lines plus the serial clock MC. The 24-bit RGB data is dithered to 18 bits by the Serializer. BUS OVERVIEW The LM2512 is a multi-lane MPL Serializer that supports a 24- bit RGB source interface ...
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... There are three bus phases on the MPL serial bus. These are 20172802 determined by the state of the MC and MD lines. The MPL bus phases are shown in Table 1. The LM2512 supports MPL Level 0 Enhanced Protocol with a Class 0 PHY. TABLE 1. Link Phases MDn State Phase Description ...
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... PCLK. A PCLK by PCLK represen- tation of these signals is duplicated on the opposite device after being transferred across the MPL Level-0 interface. The LM2512 can accommodate a wide range of display for- mats. QVGA to VGA can be supported within the 2MHz to 20 MHz PCLK input range. ...
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... See MPL DES Datasheet for details on how the specific DES handles the Frame Sequence. DITHERING FEATURE The LM2512 3-Lane MPL Serializer, 24-bit RGB input data (8-bits/color channel) is internally dithered to 18-bits (6- bits/color channel) using a high-quality stochastic dithering process. This process has a " ...
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... There are three SPI Interface signals: CSX - SPI Chip Select, SCL - SPI Clock, and SDA - SPI Data. CSX and SCL are inputs on the LM2512. SDA is a bi-directional Data line and is an input for a WRITE and an output for the READ_DATA portion of a READ operation. READs are optional and are not www ...
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... FIGURE 13. LM2512 WRITE & READ to 3-signal SPI HOST FIGURE 14. LM2512 WRITE only to 4-signal SPI HOST 13 20172888 20172889 www.national.com ...
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... Reserved, Default value recommended. Bit[2:0] 000’b = Reserved 010’ Lanes 100’ Lanes (Default) all others= Reserved Reserved 0xFF’h enables LM2512 SPI All other values disables LM2512 SPI (0x00 to 0xFE) Reserved 14 Default 00’h 00’h XX’h 00’h XX’h 00’ ...
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SPI Timing FIGURE 15. 16-bit SPI WRITE FIGURE 16. 16-bit SPI READ FIGURE 17. SPI PAGE WRITE 15 20172890 20172891 20172893 www.national.com ...
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... LUT and unlock SRA, write of 11’h to register 00’h (See LM2512 SPI Register Table). To change lanes, write of 02’h to register 0A’h. The LM2512 has the potential to pow- er-up into a condition which causes unwanted leakage current in the SRAMs. An access to each SRAM over the SPI inter- face as part of the power-up sequence is recommended in order to eliminate a potential power-up current leakage ...
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... FPD95120 by issuing a Unlock command to the FPD95120 register 16’h which also de-se- lects / locks the LM2512 SPI. After the SPI commands are completed, the MPL_PD_N signal is driven High to arm the Deserializer for the MPL start sequence. The PCLK is started up, and the SER will calibrate the DES and lock to the incom- ing PCLK signal ...
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... For PD* Input Power Down control, a GPO signal from the host is used to enable and disable the LM2512 and the DES. The LM2512 is enabled when the PD* input is High and dis- abled when the PD* input is Low. When using the auto power down mode, the PD* input needs to be held High ...
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The grounds are also useful for noise isolation and impedance control. PCB RECOMMENDATIONS General guidelines for the PCB design: • Floor plan, locate MPL SER near the connector to limit chance of cross talk to high speed serial signals. • ...
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Connection Diagram 49 UFBGA Package RGB SER Pinout SER 1 B1 SPI_SDA/ PCLK SSIO www.national.com TOP VIEW (not to scale RES1 ...
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Connection Diagram 40 LLP Package TOP VIEW (not to scale) 21 20172896 www.national.com ...
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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 49L UFBGA, 0.5mm pitch Order Number LM2512SM NS Package Number SLH49A 40L LLP, 0.5mm pitch Order Number LM2512SN NS Package Number SNA40A 22 ...
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Notes 23 www.national.com ...
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... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...