pi2eqx5864 Pericom Semiconductor Corporation, pi2eqx5864 Datasheet
pi2eqx5864
Manufacturer Part Number
pi2eqx5864
Description
5.0gbps 4-lane Pcie Gen2 Redriver With I2c Control
Manufacturer
Pericom Semiconductor Corporation
Datasheet
1.PI2EQX5864.pdf
(18 pages)
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Features
• Up to 5.0Gbps PCI Express Gen-2 Serial Re-driver
• Supporting 8 differential channels or 4 lanes of PCIe Interface
• I
• Adjustable receiver equalization and transmitter de-emphasis
• Variable input an output termination
• 1:2 channel broadcast
• Channel loop-back
• Electrical Idle fully supported
• Receiver detect and individual output control
• Single supply voltage, 1.2V ± 0.05V
• Power down modes
• Packaging: 56-contact TQFN, Pb-free & Green
Block Diagram
xyRx+
xyRx-
and output levels
xyTx+
xyTx-
2
C confi guration controls (3.3V Tolerant)
07-0277
Output
Controls
SDA
SCL
+
+
−
−
Equalizer
+
−
Data Lane Repeats 4 Times
B
A
Control registers
Input level detect
to control logic
Management
I
2
Input level detect
to control logic
& logic
C Control
Power
Equalizer
−
+
Output
Controls
+
−
RXD_x
+
−
RES_x
Mode
LB#
Ax
xxTx-
xxTx+
xyRx+
xyRx-
5.0Gbps 4-Lane PCI Express GenII Re-Driver
1
with Equalization, Emphasis, &I
Description
Pericom Semiconductor’s PI2EQX5864 is a low power,
PCI-express compliant signal re-driver. The device provides
programmable equalization, amplifi cation, and de-emphasis by
using 8 select bits, to optimize performance over a variety of
physical mediums by reducing Inter-symbol interference.
PI2EQX5864 supports eight 100-Ohm Differential CML data
I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides fl exibility with
signal integrity of the PCI-express signal before the re-driver,
whereas the integrated de-emphasis circuitry provides fl exibility
with signal integrity of the signal after the re-driver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5864 also provides power management Stand-by mode
operated by a Bus Enable pin.
Pin Confi guration
A0RX+
A1RX+
A2RX+
A3RX+
B3TX+
B0TX+
B1TX+
B2TX+
A0RX-
A1RX-
A2RX-
A3RX-
B3TX-
B0TX-
B1TX-
B2TX-
VDD
VDD
VDD
VDD
56 55 54
12
13
21 22 23
10
11
14
15
18
1
2
3
4
5
6
7
8
9
16
17
19
20
53
24
52 51 50 49
25 26 27 28
48
47
46
45
44
43
42
32
30
29
41
40
39
38
37
36
35
34
33
31
PI2EQX5864
VDD
VDD
A0TX+
A0TX-
B0RX+
B0RX-
VDD
A1TX+
A1TX-
B1RX+
B1RX-
A2TX+
A2TX-
B2RX+
B2RX-
A3TX+
A3TX-
B3RX+
B3RX-
VDD
PS8934A
2
C Control
01/21/08
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