pi2eqx5864c Pericom Semiconductor Corporation, pi2eqx5864c Datasheet
pi2eqx5864c
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pi2eqx5864c Summary of contents
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... PCI Express 2.0 ReDriver with Equalization, Emphasis, &I Description Pericom Semiconductor’s PI2EQX5864C is a low power, PCI-express compliant signal redriver. The device provides programmable equalization, amplifi cation, and de-emphasis by using 8 select bits, to optimize performance over a variety of physical mediums by reducing Inter-symbol interference. ...
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... Enables I2C control when LOW. Has internal 100K-Ohm pull-up resistor. A LVCMOS high level selects input pins control, and disables I I during startup, input status of the control pin (LB#, RES_A/B#, RXD_A/B) will be latched to set the initial register state. No Connect No Connect 2 PI2EQX5864C 2 C Control 2 C operation. Note, (Continued on Next Page) PS8934D 03/10/09 ...
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... Equalizer Confi guration The PI2EQX5864C input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) resulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-frequency signal components. Because either too little, or too much, signal compensation may be non-optimal eight levels are provided to adjust for any application. Equalizer confi ...
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... Output Confi guration The PI2EQX5864C provides fl exible output strength and emphasis controls to provide the optimum signal to pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean with good eye opening. Control of output confi gura- tion is grouped for the A and B channels, so that each channel within the group has the same setting. ...
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... Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load device on the output, the channel can be automatically enabled for operation. This allows the PI2EQX5864C to confi gure itself properly depending on the devices it is communicating with, whether 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card. ...
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... Loopback Operation Each lane of the PI2EQX5864C provides a loopback mode for test purposes which is controlled by a strapping pin and I2C register bit. The LB# pin controls all lanes together. When this pin is high normal data mode is enabled. When LB# is low the loopback mode is enabled. The fi gure below diagrams this operation. Loopback is not intended to be dynamically switched, and the normal system application is to initialize to one confi ...
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... Figure 2. Bi-directional Level Shifter Circuit 09-0050 with Equalization, Emphasis and I 27k 10k VDD2= 3.3 V Vbias = 2.4V 100nf 4. 2SK3018 2SK3018 PI2EQX5864C “Higher voltage” section 7 PI2EQX5864C 5.0Gbps 4-Lane PCI Express 2.0 ReDdriver VDD2= 3.3 V 10k 10k SDA 2 SCL 2 to I2C controller PS8934D 2 C Control 03/10/09 ...
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... Data is transferred with the most signifi cant bit (MSB) fi rst (see the I PI2EQX5864C will never hold the clock line SCL LOW to force the master into a wait state. Note: Byte-write and byte-read transfers have a fi xed offset of 0x00, because of the very small number of con- fi ...
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... Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop bit. For a write cycle, the fi rst data byte following the address byte is a dummy or fi ll byte that is not used by the PI2EQX5864C. ...
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... Equalization, Emphasis and LB_A2B2# LB_A3B3# DE_A R/W R/W R/W LB# LB INDIS_A1 INDIS_B1 INDIS_A2 R/W R/W R ODIS_A1 ODIS_B1 ODIS_A2 R/W R/W R PI2EQX5864C 2 C Control DE_B rsvd rsvd R INDIS_B2 INDIS_A3 INDIS_B3 R/W R/W R ODIS_B2 ODIS_A3 ODIS_B3 R/W R/W R ...
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... PD_A1# PD_B1# PD_A2# R/W R/W R RXD_A1 RXD_B1 RXD_A2 R/W R/W R SEL2_A D0_A D1_A R/W R/W R PI2EQX5864C 2 C Control RES_B2# RES_A3# RES_B3# R/W R/W R PD_B2# PD_A3# PD_B3# R/W R/W R RXD_B2 RXD_A3 RXD_B3 R/W R/W R ...
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... A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defi nes a STOP condition, as shown in the fi gure below. 09-0050 5.0Gbps 4-Lane PCI Express 2.0 ReDdriver with Equalization, Emphasis and SEL2_B D0_B D1_B R/W R/W R PI2EQX5864C 2 C Control D2_B S0_B S1_B R/W R/W R PS8934D 03/10/09 ...
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... I2C application, an offset address byte will be presented at the second byte in write command, which is called dummy byte here and will be simply ignored in this application for correct interoperation. 13 PI2EQX5864C 2 NO ACK DATA OUT N ACK ACK DATA IN N ...
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... A Conditions = 0 TO 70°C) A Conditions 14 PI2EQX5864C 5.0Gbps 4-Lane PCI Express 2.0 ReDdriver Note: Stresses greater than those listed under MAX I MUM RAT- INGS may cause permanent damage to the de vice. This is a stress rating only and func tion tion of the device at these or any other conditions above those indicated in the operational sections of this spec i fi ...
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... Conditions Single ended |VTX-D+ - VTX-D-| VTX-DIFFP VTX-D+ - VTX- VTX-D+ + VTX- 20% to 80% ( 70°C) A Conditions Min. VDD/2 +0.2 -0 4mA VDD-0 4mA OL 0.2 -20 -20 15 PI2EQX5864C 2 C Control Min. Typ. Max. 0.3 0.2 1.5 Min. Typ. Max 100 120 200 1000 0.4 2.0 VDD- 0.3 150 ...
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... A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the V region of the falling edge of SCL. 09-0050 with Equalization, Emphasis and I = 1.2 ± 0.05v 70° Conditions I = 3mA OL Conditions levels. 16 PI2EQX5864C 5.0Gbps 4-Lane PCI Express 2.0 ReDdriver Min. Typ. Max. 1 0.3 DD -0.3 0.7 0.4 0.2 (1) Min. ...
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... START SDA t SU;DAT LOW SCL t HD;STA t HD;DAT S 09-0050 5.0Gbps 4-Lane PCI Express 2.0 ReDdriver with Equalization, Emphasis and HD;STA t SU;STA HIGH Sr I2C Timing Channel Latency, 5.0 Gbps 17 PI2EQX5864C 2 C Control STOP START BUF t SU;STO P S PS8934D 03/10/09 ...
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... Output Level Settings (1V left, and 0.5V right at 5.0 Gbps) 0.0 dB (Dx = 000) –6.5 dB (Dx = 101) Output De-Emphasis Characteristics 09-0050 5.0Gbps 4-Lane PCI Express 2.0 ReDdriver with Equalization, Emphasis and I –3.5 dB (Dx = 010) –8.5 dB (Dx = 111) 18 PI2EQX5864C 2 C Control PS8934D 03/10/09 ...
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... Eye Diagrams 5.0Gbps (input left, output right) Data Waveforms, 2.5Gbps (left) & 5.0Gbps (right) Signal Source Connector AC Test Circuit Referenced in the Electrical Characteristic Table 09-0050 5.0Gbps 4-Lane PCI Express 2.0 ReDdriver with Equalization, Emphasis and I FR4 A B SmA SmA Connector ≤ PI2EQX5864C 2 C Control C D.U.T. In Out PS8934D 03/10/09 ...
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... Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 09-0050 5.0Gbps 4-Lane PCI Express 2.0 ReDdriver with Equalization, Emphasis and I DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN) PACKAGE CODE: ZF56 DOCUMENT CONTROL #: PD-2024 Package Code Package Description ZF Pb-free & Green 56-Contact TQFN 20 PI2EQX5864C 2 C Control DATE: 05/15/08 REVISION: C PS8934D 03/10/09 ...