px1011b NXP Semiconductors, px1011b Datasheet
px1011b
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px1011b Summary of contents
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... PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1011B PCI Express PHY is compliant to the PCI Express Base Specification, Rev. 1.0a , and Rev. 1.1 . The PX1011B includes features such as Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and provides superior performance to the Media Access Control (MAC) layer devices ...
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... PX1011B_2 Product data sheet Quick reference data Conditions for JTAG I/O for SSTL_2 I/O for core for high-speed serial I/O and PVT for serializer for serializer operating commercial industrial Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Min Typ Max Unit 3.0 3.3 3.6 V 2.3 2.5 2.7 V 1.15 1.2 1 ...
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... NXP Semiconductors 4. Ordering information Table 2. Ordering information Type number Solder process PX1011B-EL1/G Pb-free (SnAgCu solder ball compound) PX1011BI-EL1/G Pb-free (SnAgCu solder ball compound) 5. Marking Table 3. Line Marking A PX1011B-EL1/G PX1011BI-EL1/G B xxxxxxx C 2PGyyww [1] Industrial temperature range. PX1011B_2 Product data sheet Package Name Description LFBGA81 plastic low profi ...
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... Ln_TxData0 Ln_TxData1 8b/10b ENCODE PARALLEL TO SERIAL 250 MHz clock CLK GENERATOR TX I/O REFCLK I/O TX_P TX_N REFCLK_P REFCLK_N Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY PCI Express MAC RXDATA [ 7:0 ] RESET_N PCI Express PHY REGISTER 8 10b/8b DECODE ELASTIC BUFFER 10 K28.5 SERIAL DETECTION TO ...
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... DDD1 DDD1 DDD3 TCK TRST_N V V DDD3 DDD3 TDI DDD2 TDO TXIDLE V PWRDWN0 SS RXPOL TXCOMP PWRDWN1 Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY RXDATAK RXCLK RXSTATUS0 RXDATA0 V RXSTATUS1 SS V RXVALID RXSTATUS2 SS DDD2 V PHYSTATUS TXDATA0 ...
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... J4 input SSTL_2 J3 input SSTL_2 H6 input SSTL_2 J6 input SSTL_2 Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Table 4 to Table 11. Note that input and Description differential input receive pair with 50 on-chip termination differential output transmit pair with 50 on-chip termination Description 8-bit transmit data input from the MAC ...
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... V CMOS G3 input 3.3 V CMOS H3 output 3.3 V CMOS Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Description indicates symbol lock and valid data on RX_DATA and RX_DATAK used to communicate completion of several PHY functions including power management state transitions and receiver detection indicates receiver detection of an electrical idle; ...
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... Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection. The PXPIPE interface between the MAC and PX1011B is a superset of the PHY Interface for the PCI Express (PIPE) specification. The following feature have been added: • ...
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... The PLL has a sufficiently high bandwidth to handle a 100 MHz reference clock with a 30 kHz to 33 kHz spread spectrum. 8.3 Clocking There are three clock signals used by the PX1011B: • REFCLK is a 100 MHz external reference clock that the PHY uses to generate the 250 MHz data clock and the internal bit rate clock ...
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... L1.idle state of the Link Training and Status State Machine (LTSSM). • P2 state: PHY will enter P1 instead. PX1011B_2 Product data sheet PCI Express stand-alone X1 PHY 100 MHz Rev. 02 — 19 March 2008 PX1011B 250 MHz 002aac172 © NXP B.V. 2008. All rights reserved ...
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... SKP symbol. PX1011B_2 Product data sheet Transmitter Receiver [ [2] idle idle [2] idle idle - - 10b 000b 011b Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY TX PLL RXCLK RX PLL/CDR off - - - 000b 002aac173 © NXP B.V. 2008. All rights reserved. ...
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... RXDET_LOOPB, asserts TXIDLE and changes the POWERDOWN signals to state P1. PX1011B_2 Product data sheet Figure 6 shows example timing for beginning loopback. In this TXCLK Tx-m Tx-n RXCLK Rx-c Rx-d Figure 7 shows an example of switching from loopback mode to Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Tx-o Tx-p Tx-q Rx-e Rx-f Rx-g Tx-m Tx-n Rx-e 002aac174 © NXP B.V. 2008. All rights reserved ...
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... Looped back RX data Figure 8 shows an example of timing for entering electrical idle. ScZero COM IDL active (ends with Electrical Idle ordered-set) Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Junk 001aac785 002aac175 © NXP B.V. 2008. All rights reserved ...
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... active COM 000b 001b Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Function description normal operation transmitter in idle loopback mode illegal illegal transmitter in idle illegal transmitter in idle receiver detect SKP SKP active 000b 001aac779 © ...
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... Elastic buffer overflow 3. Elastic buffer underflow 4. Disparity error PX1011B_2 Product data sheet active COM 000b 010b Function table PXPIPE status interface signals Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY SKP active 000b 002aac176 Output pin RXSTATUS2 RXSTATUS1 RXSTATUS0 ...
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... EDB is presented on the parallel interface. PX1011B_2 Product data sheet Rx-a Rx-b EDB 000b 100b Rx-a Rx-b Rx-c 000b 111b Figure 13, the PHY is receiving a repeating set of Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Rx-d Rx-e 000b 001aac780 Rx-d Rx-e 000b 001aac781 © NXP B.V. 2008. All rights reserved ...
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... RXCLK RXDATA[7:0] RXVALID RXPOL Fig 15. Polarity inversion PX1011B_2 Product data sheet Rx-a Rx-b Rx-c 000b Rx-a Rx-b Rx-c 000b D21.5 D21.5 Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY EDB Rx-d 110b 000b 001aac782 Rx-e Rx-f 101b 000b 001aac783 D10.2 D10.2 001aac786 © NXP B.V. 2008. All rights reserved ...
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... If JTAG is not planned to be used recommended to pull down TRST_N to V PX1011B_2 Product data sheet data K28.5 K28.5 valid data . SS Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY K28.5 K28.5 byte transmitted with negative disparity K28.5 K28.5 002aac177 © NXP B.V. 2008. All rights reserved ...
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... Product data sheet Limiting values Conditions for JTAG I/O for SSTL_2 I/O for core for high-speed serial I/O and PVT for serializer for serializer HBM CDM operating commercial industrial Thermal characteristics Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Min Max Unit 0.5 +4.6 V 0.5 +3.75 V 0.5 +1.7 V 0.5 +1.7 V ...
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... SSTL_2 I/O for core for high-speed serial I/O and PVT for serializer for serializer for JTAG I/O for SSTL_2; no load for core for high-speed serial I/O and PVT for serializer for serializer 1 clock cycle Rev. 02 — 19 March 2008 PX1011B Min Typ Max Unit 3.0 3.3 3.6 V 2.3 2.5 2.7 V 1.15 1.2 1 ...
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... Figure 17 at falling edge; measured from +150 mV to 150 mV on the differential waveform; Figure 17 on pin REFCLK_N and pin REFCLK_P 1 clock cycle Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Min Typ Max Unit 0.6 - 4.0 V/ns 0 ...
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... Figure 18 see Figure 18 see Figure 18 see Figure 18 TXCLK PXPIPE INPUT t su(TX)(PXPIPE) RXCLK PXPIPE OUTPUT t su(RX)(PXPIPE) Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY dV/dt at falling edge V = +150 150 mV IL 002aad694 Min Typ Max 249.925 250 250.075 249.925 250 250 ...
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... T amb Fig 20. Non transition eye PX1011B_2 Product data sheet 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.2 0.1 0 0.1 0.2 0.3 0 nominal V DD 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.2 0.1 0 0.1 0.2 0.3 0 nominal V DD Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY 001aac789 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 unit intervals 001aac790 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 unit intervals © NXP B.V. 2008. All rights reserved ...
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... 9.1 6.4 6.4 0.12 0.8 0.15 0.08 8.9 REFERENCES JEDEC JEITA MO-205 - - - Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY SOT643 detail 0.1 EUROPEAN ISSUE DATE PROJECTION 00-11-01 02-03-28 © NXP B.V. 2008. All rights reserved ...
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... Solder bath specifications, including temperature and impurities PX1011B_2 Product data sheet PCI Express stand-alone X1 PHY Rev. 02 — 19 March 2008 PX1011B © NXP B.V. 2008. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 22. Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Figure 22) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... Peripheral Component Interconnect Physical Coding Sub-layer PHYsical layer Phase-Locked Loop PHY Interface for the PCI Express Process Voltage Temperature Serial to Parallel Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY peak temperature time 001aac844 © NXP B.V. 2008. All rights reserved ...
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... Max value changed from “80 ps” to “-” TX_FALL Figure 17 “Differential measurement points” “Disclaimers”: added “Quick reference data” disclaimer Objective data sheet - Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY Supersedes PX1011B_1 ”, “dV/dt”, “V ”, “V ”, “ ” C- REFCLK - © ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 19 March 2008 PX1011B PCI Express stand-alone X1 PHY © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: PX1011B_2 PX1011B All rights reserved. Date of release: 19 March 2008 ...