qlx4600-sl30 Intersil Corporation, qlx4600-sl30 Datasheet
qlx4600-sl30
Related parts for qlx4600-sl30
qlx4600-sl30 Summary of contents
Page 1
... If the serial bus is used, all 32 compensation levels are available. Operating on a single 1.2V power supply, the QLx4600-SL30 enables per channel throughputs 6.25Gb/s while supporting lower data rates including 5, 4.25, 3.125, and 2.5Gb/s. The QLx4600-SL30 uses current mode logic (CML) inputs/outputs and is packaged in a 4mmx7mm 46 lead QFN ...
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... IPC/JEDEC J STD-020. Pin Configuration 2 QLx4600-SL30 TEMP. RANGE (° + QFN 7” Prod. Tape & Reel; Qty 1,000 QFN 7” Sample Reel; Qty 100 QLx4600-SL30 (46 LD 4x7 QFN) TOP VIEW IN1[ IN1[N] ...
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... Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. OUT1[N,P] 36, 37 Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. BGREF 38 External bandgap reference resistor. Recommended value of 6.04kΩ ±1%. 3 QLx4600-SL30 DESCRIPTION FN6981.1 November 19, 2009 ...
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... Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data latched on the rising clock edge. Clock speed is recommended to be between 10MHz and 20MHz. Internally pulled down. EXPOSED - Exposed ground pad. For proper electrical and thermal performance, this pad should be PAD connected to the PCB ground plane. 4 QLx4600-SL30 DESCRIPTION FN6981.1 November 19, 2009 ...
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... Resistance DC Single-Ended Input Resistance Input Return Loss (Differential) 5 QLx4600-SL30 Thermal Information Thermal Resistance (Typical QFN Package (Note 1 Operating Ambient Temperature Range 0°C to +70°C Storage Ambient Temperature Range . . . . . -55°C to +150°C Maximum Junction Temperature +125°C Pb-Free Reflow Profile see link below http://www ...
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... Lane-to-Lane Skew Propagation Delay LOS Assert Time LOS De-Assert Time Data-to-Line Silence t DS Response Time 6 QLx4600-SL30 = 1.2V +25°C, and 1.1V to 1.3V 0°C to +70°C. (Continued CONDITION 50MHz to 3.75GHz 50MHz to 3.75GHz Active data transmission mode; Measured differentially at OUT[k]P and OUT[k]N with 50Ω ...
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... Timing Difference (SAS NOTES: 3. After channel loss, differential amplitudes at QLx4600-SL30 inputs must meet the input voltage range specified in “Absolute Maximum Ratings” on page 5. 4. Temperature = +25° 1.2V Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted signal (as measured at the input to the channel) ...
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... The loss characteristics of these test channels are plotted as a function of frequency in Figure 2. The received signal at the output of these test channels was then processed by the QLx4600-SL30 before being passed to a receiver. Eye diagram measurements were made with 4000 waveform acquisitions and include random jitter ...
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... TWIN-AXIAL CABLE (CABLE C) (NOTE 13), 5Gb/s 9 QLx4600-SL30 (Continued) FIGURE 5. QLx4600-SL30 OUTPUT AFTER 20m OF 24AWG TWIN-AXIAL CABLE (CABLE A), 5Gb/s FIGURE 7. QLx4600-SL30 OUTPUT AFTER 12m OF 30AWG TWIN-AXIAL CABLE (CABLE B), 5Gb/s FIGURE 9. QLx4600-S30 OUTPUT AFTER 20m OF 28AWG TWIN-AXIAL CABLE (CABLE C) (NOTE 13), 5Gb/s 40ps/div 40ps/div 40ps/div FN6981 ...
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... FIGURE 14. RECEIVED SIGNAL AFTER 40" FR4, 6.25Gb/s 10 QLx4600-SL30 (Continued) FIGURE 11. QLx4600-SL30 OUTPUT AFTER 30m OF 24AWG TWIN-AXIAL CABLE (NOTE 13), 5Gb/s FIGURE 13. QLx4600-SL30 OUTPUT AFTER 15m OF 28AWG TWIN-AXIAL CABLE (CABLE D) (NOTE 13), 6.25Gb/s FIGURE 15. QLx4600-SL30 OUTPUT AFTER 40" FR4, 6.25Gb/s 40ps/div 32ps/div 32ps/div FN6981.1 November 19, 2009 ...
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... FIGURE 16. INPUT COMMON-MODE RETURN LOSS 0 -5 -10 -15 -20 -25 -30 -35 0 0.5 1 1.5 2 Frequency (GHz) FIGURE 18. INPUT DIFFERENTIAL RETURN LOSS FIGURE 20. DIFFERENTIAL CROSSTALK BETWEEN ADJACENT INPUT CHANNELS NOTE: 13. Differential transmit amplitude = 1200mV 11 QLx4600-SL30 (Continued -10 -15 -20 -25 -30 2.5 3 3.5 4 FIGURE 17. OUTPUT COMMON-MODE RETURN LOSS 0 -5 -10 -15 -20 Channel 1 -25 ...
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... IN[k] [P,N] FIGURE 22. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE QLx4600-SL30 Operation The QLx4600-SL30 is an advanced quad lane-extender for high-speed interconnects. A functional diagram of one of the four channels in the QLx4600-SL30 is shown in Figure 22. In addition to a robust equalization filter to compensate for channel loss and restore signal fidelity, ...
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... Line silence is commonly broken by the limiting amplification in other equalizers. This disruption can be detrimental in many systems that rely on line silence as part of the protocol. The QLx4600-SL30 contains special lane management capabilities to detect and preserve periods of line silence while still providing the fidelity- enhancing benefits of limiting amplification during active data transmission ...
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... Each 5-bit word determines which of 32 boost levels to use for the corresponding equalizer. Register 1 instructs the QLx4600-SL30 to use registers 2 through 21 to set the boost level rather than the control pins CP[k][A,B,C]. Both options have their relative advantages. The control ...
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... Control Pin Boost Setting When register 1 of the QLx4600-SL30 is zero (the default state on power-up), the voltages at the CP pins are used to determine the boost level of each channel. For each of the four channels, k, the [A], [B], and [C] control pins (CP[k]) are associated with a 3-bit non binary word. ...
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... QLx4600-SL30. Figure 27 shows an exemplary timing diagram for the signals on these pins. The serial bus can be used to program a single QLx4600-SL30 according to the following steps: 1. The ENB pin is pulled ‘LOW’. - While this pin is ‘LOW’, the data input on DI are read into registers but not yet latched ...
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... ENB t CLK DI FIGURE 27. TIMING DIAGRAM FOR PROGRAMMING THE INTERNAL REGISTERS OF THE QLx4600-SL30 Programming Multiple QLx4600-SL30 Devices The serial bus interface provides a simple means of setting the equalizer boost levels with a minimal amount of board circuitry. Many of the serial interface signals can be shared among the QLx4600-SL30 devices on a board and two options are presented in this section ...
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... Clock ENB FIGURE 30. SERIAL BUS PROGRAMMING MULTIPLE QLx4600-SL30 DEVICES USING DI/DO CARRYOVER ENB t SCK CLK t t SDI HDI DI R21 R20 QLx4600-SL30 (D) FIGURE 31. TIMING DIAGRAM FOR PROGRAMMING MULTIPLE QLx4600-SL30 DEVICES USING DI/DO CARRYOVER 18 QLx4600-SL30 20 Clock Cycles st 21 Rising Edge t CQ QLx4600-SL30 QLx4600-SL30 (B) ENB DI ENB ...
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... Detection Threshold (DT) Pin Functionality The QLx4600-SL30 is capable of maintaining periods of line silence on any of its four channels by monitoring each channel for loss of signal (LOS) conditions and subsequently muting the outputs of a respective channel when such a condition is detected. A reference current applied to the detection threshold (DT) pin is used to set the LOS threshold of the internal signal detection circuitry ...
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... Typical Application Reference Designs Figures 33 and 34 show reference design schematics for a QLx4600-SL30 evaluation board with an SMA connector interface. Figure 33 shows the schematic for the case when the equalizer boost level is set via the CP pins. Figure 34 shows the schematic for the case when the level is set via the serial bus interface. ...
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... Typical Application Reference Designs Figures 33 and 34 show reference design schematics for a QLx4600-SL30 evaluation board with an SMA connector interface. Figure 33 shows the schematic for the case when the equalizer boost level is set via the CP pins. Figure 34 shows the schematic for the case when the level is set via the serial bus interface. ...
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... Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 22 QLx4600-SL30 www.intersil.com/product_tree www.intersil.com/design/quality www.intersil.com FN6981.1 ...
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... LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN) Rev 0, 9/09 4.00 6 PIN 1 INDEX AREA (4X) 0.05 TOP VIEW 0.70 ±0.05 SIDE VIEW ( 3. 2.50 5.50 ) TYPICAL RECOMMENDED LAND PATTERN 23 QLx4600-SL30 A B SIDE VIEW SEE DETAIL "X" 0. SEATING PLANE 0.05 C NOTES: 1. Dimensions are in millimeters. Dimensions Dimensioning and tolerancing conform to AMSE Y14.5m-1994. ...