ncn6000 ON Semiconductor, ncn6000 Datasheet

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ncn6000

Manufacturer Part Number
ncn6000
Description
Compact Smart Card Interface Ic
Manufacturer
ON Semiconductor
Datasheet

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NCN6000
Compact Smart Card
Interface IC
interface applications. The device handles any type of smart card
through a simple and flexible microcontroller interface. On top of that,
due to the built−in chip select pin, several couplers can be connected in
parallel. The device is particularly suited for low cost, low power
applications, with high extended battery life coming from extremely
low quiescent current.
Features
Typical Application
**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 4
Techniques Reference Manual, SOLDERRM/D.
The NCN6000 is an integrated circuit dedicated to the smart card
Card Operation
Single External Low Cost Inductor only, providing a High Efficiency
Power Conversion
Integrity on both the Card I/O and the Signal Lines
Feedback to External CPU
Going Input
High or Low State
100% Compatible with ISO7816−3 and EMV Standard
Wide Battery Supply Voltage Range: 2.7 v Vbat v 6.0 V
Programmable CRD_VCC Supply to Cope with either 3.0 V or 5.0 V
Built−in DC−DC Converter Generates the CRD_VCC Supply with a
Full Control of the Power Up/Down Sequence Yields High Signal
Programmable Card Clock Generator
Built−in Chip Select Logic allows Parallel Coupling Operation
ESD Protection on Card Pins (8.0 kV, Human Body Model)
Fault Monitoring includes Vbat
Card Detection Programmable to Handle Positive or Negative
Built−in Programmable CRD_CLK Stop Function Handles both
These are Pb−Free Devices**
E−Commerce Interface
ATM Smart Card
Pay TV System
CONTROLLER
MICRO
Figure 1. Simplified Application
SMART CARD
INTERFACE
NCN6000
low
and Vcc
low,
providing Logic
ISO/EMV
1
NCN6000DTB
NCN6000DTBG
NCN6000DTBR2
NCN6000DTBR2G TSSOP−20* 2500/Tape & Reel
†For information on tape and reel specifications,
*This package is inherently Pb−Free.
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
CLOCK_IN
PWR_ON
Device
STATUS
(Note: Microdot may be in either location)
RESET
1
PGM
INT
ORDERING INFORMATION
CS
I/O
A0
A1
A
L
Y
W
G
PIN CONNECTIONS
10
http://onsemi.com
2
3
4
5
6
7
8
9
1
DTB SUFFIX
CASE 948E
TSSOP−20
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
TSSOP−20*
TSSOP−20*
TSSOP−20* 2500/Tape & Reel
(Top View)
Package
Publication Order Number:
20
1
17
12
20
19
18
16
15
14
13
11
MARKING
DIAGRAM
75 Units / Rail
75 Units / Rail
Shipping
V
L
L
PWR_GND
GROUND
CRD_V
CRD_IO
CRD_CLK
CRD_RST
CRD_DET
ALYWG
NCN6000/D
out_
out_
bat
NCN
6000
G
H
L
CC

Related parts for ncn6000

ncn6000 Summary of contents

Page 1

... NCN6000 Compact Smart Card Interface IC The NCN6000 is an integrated circuit dedicated to the smart card interface applications. The device handles any type of smart card through a simple and flexible microcontroller interface. On top of that, due to the built−in chip select pin, several couplers can be connected in parallel ...

Page 2

... STATUS 6 PB2 CS CRD_V 7 PB1 CRD_IO RESET 8 PB0 CRD_CLK I/O 9 IRQ CRD_RST INT 10 CLOCK_IN CRD_DET XTAL NCN6000 MCU GND GND Figure 2. Typical Application http://onsemi.com NCN6000 bat GND 15 C3 100 Swa GND 13 18 Swb 12 ...

Page 3

... PGM CLOCK_IN 4 PWR_ON V bat STATUS GND V bat_OK I RESET NCN6000 V bat_OK 500 Delay R CARD DETECTION POLARITY PROGRAMMABLE CLK STOP F CLOCK out DC−DC CONVERTER DATA DECODER SELECT 1: Set_V CC 1/1 Active Pwr_Down 1/2 CLOCK 1/4 ...

Page 4

... NCN6000 http://onsemi.com 4 ...

Page 5

... Insertion and Extraction of the card. The MPU shall clear the INT line when the card has been extracted, making the interrupt function available for other purposes. However, neither the NCN6000 operation nor the smart card I/O line or commands are affected by the state of the INT pin. ...

Page 6

... Note: The PWR_ON bit must be combined with a Low state CS signal to activate the function. (Table 2) This pin provides logic state related to the card and NCN6000 status. According to the A0, A1 and PGM logic state, this pin carries either the Card present status or the Vbat or the DC− ...

Page 7

... Normally Open switch, negative going insertion detection. The Normally Closed switch, positive going insertion detection, can be defined by programming the NCN6000 accordingly. In this case, the polarity must be set up during the first cycles of the system initialization, otherwise an already inserted card will not be detected by the chip. ...

Page 8

... Maximum electrical ratings are defined as those values beyond which damage to the device may occur This current represents the maximum peak current the pin can sustain, not the NCN6000 consumption (see Ibat 3. Human Body Model 1500 100 pF. ...

Page 9

... ESR capacitor in parallel, to reduce both the high frequency noise and ripple to a minimum. Depending upon the PCB layout, it might be necessary is to use two 6.8 mF/10 V/ceramic/X7R//SMD1206 in parallel, yielding an improved CRD_VCC ripple over the temperature range. 6. According to ISO7816−3, paragraph 4.3.2. NCN6000 Symbol Pin Min ...

Page 10

... OH Output High Voltage = 200 mA STATUS, INT @ Since pull up resistor is provided by the NCN6000, the external MPU can use an Open Drain connection. DIGITAL PARAMETERS SECTION @ 2.70 VvVbatv6.0 V, CHIP PROGRAMMING MODE temperature, unless otherwise noted.) Rating A0, A1, PGM, PWR_ON, RESET and I/O Data Set Up Time ...

Page 11

... Operation Mode @ Vcc = 3 Vcc = 5 The CRD_CLK clock can operate MHz, but the rise and fall time are not guaranteed to be fully within the ISO7816 specification over the temperature range. Typically, tr and tf are CRD_CLK = 10 MHz. NCN6000 Symbol Pin ...

Page 12

... Programming and Status Functions The NCN6000 features a programming interface and a status interface. Figure 4 illustrates the programming mode. Table 1. Programming and Status Functions Pinout Logic CRD_VCC CLOCK_IN Prg. 3.0 V/5.0 V Divide Ratio Pins Name 5 STATUS Not Affected Not Affected 6 CS Latch On Rising Edge Rising Edge ...

Page 13

... The CRD_VCC and CRD_CLK are not affected when the NCN6000 operates outside their respective decoded logic address. 13. The High Level on STATUS in registers $00 to $0F, inclusive, having being implemented to reduce current consumption but have no other meanings. 14. At turn on, the NCN6000 is initialized with CRD_VCC = 3.0V, CLOCK_IN Ratio = 1/1, CRD_CLK = START, CRD_DET = Normally Open. NCN6000 is state 1: asynchronous clock, ratio 1/1, CRD_CLK active, CRD_DET = Normally Open, CRD_VCC = 3 ...

Page 14

... DC−DC Converter and Card Detector Status The NCN6000 status can be polled when Please consult Figures 4 and 5 for a description of input and output signals. The status message is described in Table 4. Note: in order to cope with a start up under low battery condition, the Vbat OK message uses a negative logic as depicted here below. Table 4. Card and DC− ...

Page 15

... NCN6000 does not take any further responsibility in the data transaction. When the chip operates in the programming mode, the NCN6000 provide a flexible access to set up the CRD_VCC voltage, the CRD_CLK and the CRD_DET smart card signals. The external microcontroller takes care of the smart card transaction and shall handle the interface accordingly ...

Page 16

... A0 A1 RESET CS Active Mode In the active mode, the NCN6000 is selected by the external MPU and the STATUS pin can be polled to get the status of either the DC−DC converter or the presence of the card (inserted or not valid). The power is not connected to the card: CRD_VCC = 0 V. ...

Page 17

... Transaction Mode During the transaction mode, the NCN6000 maintains power supply and clock signal to the card. All the signal levels related with the card are translated as necessary to cope with the MPU and the card. The DC−DC converter status and the Vbat state can be monitored on the STATUS by using the A0 and A1 logic inputs as depicted in Tables 3 and 4 ...

Page 18

... CARD EXTRACTION DETECTED CRD_VCC Voltage CRD_CLK CRD_RST CRD_IO Figure 9. Typical Power Down Sequence in the NCN6000 Interface Figure 10. Power Down Sequence Details NCN6000 Digital Filter Delay (50 ms min) http://onsemi.com 18 CRD_VCC CRD_RST CRD_CLK CRD_IO ...

Page 19

... CRD_VCC supply. When a card is inserted, the detector circuit asserts INT = Low as depicted before. When the NCN6000 detects a card extraction, the power down sequence is activated, regardless of the PWR_ON state, and the INT pin is asserted Low ...

Page 20

... Note: since the internal pull up resistor is relatively high (500 kW typical), one must use input impedance probe to read this signal. CRD_DET Input Voltage (card inserted) on the internal behavior of the NCN6000, but will be automatically cleared when the DC−DC will be activated by the MPU (CS=L, PWR_ON = Positive High transition) http://onsemi.com ...

Page 21

... The logic level of the data lines are asserted High or Low, depending upon the state forced by the external MPU, when the start up sequence is completed. Under no situation the NCN6000 shall launch automatically a smart card ATR sequence. Assuming PWR_ON = H, the CRD_VCC voltage CS PWR_ON ...

Page 22

... The built−in comparator, associated with the band gap reference, continuously monitors the +Vbat input. During the start up, all the NCN6000 functions are deactivated and no data transfer can take place. When the +Vbat voltage rises above 2.35 V (typical), the chip is activated and all the functions becomes available ...

Page 23

... W, thus yielding high losses during the DC−DC operation, depending upon the technology used to build the capacitor. NCN6000 oscillogram, Figure 18, depicts the DC−DC behavior under these two modes of operation. Beside the DC−DC converter, NMOS Q4 provides a low ...

Page 24

... Based on the experiments carried out during the NCN6000 characterization, the best comprise, at time of printing this document, is 6.8 mF/10 V/Ceramic/X7R capacitor in parallel to achieve the CRD_VCC filtering. The ESR will not extend 50 mW over the temperature range and the combination of standard parts provide an acceptable –20% to +20% tolerance, Table 5 ...

Page 25

... Card operating frequency from the external clock source. 3. Controls the clock state according to the smart card specification. In addition, the NCN6000 adjusts the signal coming from the microprocessor to get the Duty Cycle window as defined by the ISO7816−3 specification. The logic input pins A0, A1, PGM, I/O and RESET fulfill ...

Page 26

... The clock can be re−programmed without halting the rest of the circuit, whatever be the new clock divider ratio. In NCN6000 activated before the CRD_CLK signal has been updated. Generally speaking, such a delay can be derived from the ...

Page 27

... The CRD_CLK signal is halted in the High logic state, following the Chip Select positive going transition. Logic Input conditions: The CRD_CLK signal is halted in the Low logic state, following the Chip Select positive going transition. Logic Input conditions: NCN6000 Figure 26. Command Stop Clock HIGH PGM = Low RESET = Low I/O = Low Figure 27 ...

Page 28

... Since the CRD_CLK signal can generate very fast transient (i. 2 pF), adapting the design to cope with the EMV noise specification might be necessary at final check out. Using an external RC network is a way to reduce the dv/dt, hence the EMI noise. NCN6000 PGM = Low RESET = High I/O = Low Figure 29 ...

Page 29

... Seq 1 Figure 30. Basic Internal I/O Level Shifter Note: The I/O data depends solely upon the smart card ATR content, the NCN6000 being not involved in these data. Figure 32. Typical I/O and RST Signals During an ATR Sequence. NCN6000 mechanism is useful to force the CRD_IO card pin in either a High or a Low pre− ...

Page 30

... V ON OFF Figure 33. Typical Schmitt Trigger Characteristic Interrupt Function The NCN6000 flags the external microprocessor by pulling down the INT signal provided in pin 9. This signal is activated by one of the here below referenced operations. Table 6. Interrupt Functions Pin Related Card Insertion and 11 Extraction DC− ...

Page 31

... Normally Open avoid this direct sink to ground from the battery. Parallel Operation When two or more NCN6000 operate in parallel on a common digital bus, the Chip Select pin allows the selection of one chip from the bank of the paralleled devices. Of course, the external MPU shall provide one unique CS line for each of the NCN6000 considered interfaces ...

Page 32

... T0 operation. Provisions are made to provide a communication link with an external computer by using the RS232 standard port. Due to the Chip Select signal, several NCN6000 can share a common data bus as depicted in Figure 36. In this example, two interfaces are connected to a single MPU, the CS pins being controlled by two different signals ...

Page 33

... R20 RESET 4 GND IN R21 GND 4 VCC MC34164 R16 220 R C11 R16 2.2 mF 220 SW13 RESET GND Figure 35. NCN6000 Single Interface Demo Board NCN6000 GND 10k VCC 1 9 I/O PC0 10 A0 PC1 11 A1 PC2 12 RESET PC3 13 PGM PC4 14 PWR_ON ...

Page 34

... SW DIP−2 IN R10 1 = Mode B GND 4 Mode R16 MC34164 220 R C11 R16 2.2 mF 220 SW13 RESET C10 4.7 mF/10 V GND C9 4.7 mF/10 V Figure 36. NCN6000 Single Interface Demo Board NCN6000 GND 10k VCC 1 9 I/O PC0 10 A0 PC1 11 A1 PC2 12 RESET PC3 13 PGM ...

Page 35

... Basic internal I/O Level Shifter 31 Typical CRD_IO Rise Time 32 Typical I/O and RST Signals During an ATR Sequence 33 Typical Schmitt Trigger Characteristic 34 Typical Single Sided Printed Circuit Board Layout 35 NCN6000 Single Interface Demo Board 36 Typical Dual Interface Application http://onsemi.com 35 Title Page ...

Page 36

... G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCN6000/D ...

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