gtl2007pw NXP Semiconductors, gtl2007pw Datasheet
gtl2007pw
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gtl2007pw Summary of contents
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GTL2007 12-bit GTL to LVTTL translator with power good control Rev. 02 — 16 February 2007 1. General description The GTL2007 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL ...
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... ref t PLH t PHL 4. Ordering information Table +85 C. amb Type number GTL2007PW GTL2007_2 Product data sheet 12-bit GTL to LVTTL translator with power good control Quick reference data Parameter Conditions input/output capacitance A port port 1 LOW-to-HIGH nA to nB; see propagation delay nBI to nAO ...
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... NXP Semiconductors 5. Functional diagram GTL2007 1 GTL VREF 2 1AO LVTTL outputs 3 2AO 4 5A LVTTL inputs/outputs (open-drain LVTTL input EN1 7 GTL input 11BI LVTTL input/output 8 11A (open-drain) 9 GTL input 9BI 10 3AO LVTTL outputs 11 4AO 12 10AI1 LVTTL inputs 13 10AI2 (1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs ...
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... GTL2007_2 Product data sheet 12-bit GTL to LVTTL translator with power good control VREF 1 2 1AO 3 2AO EN1 11BI 7 GTL2007PW 11A 8 9BI 9 10 3AO 4AO 11 10AI1 12 13 10AI2 GND 14 Pin description Pin Description 1 GTL reference voltage 2 ...
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... NXP Semiconductors Table 3. Symbol 6BI 5BI 11BO EN2 7BO2 7BO1 2BI 1BI Functional description Refer to 7.1 Function tables Table HIGH voltage level LOW voltage level. Input 1BI/2BI/3BI/4BI/9BI L H [1] 1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in Table Table 5 ...
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... NXP Semiconductors Table HIGH voltage level LOW voltage level. Input 10AI1/10AI2 Table HIGH voltage level LOW voltage level. Input 5BI/6BI [1] The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs ...
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... NXP Semiconductors 8. Application design-in information 1 1.2 k 1.5 k PLATFORM HEALTH MANAGEMENT CPU1 1ERR_L CPU1 THRMTRIP L CPU1 PROCHOT L CPU2 PROCHOT L NMI_L CPU2 1ERR_L CPU2 THRMTRIP L CPU1 SMI L CPU2 SMI L SMI_BUFF_L SOUTHBRIDGE NMI SOUTHBRIDGE SMI_L power supply POWER GOOD Fig 3. Typical application ...
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... NXP Semiconductors 9. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I LOW-level output current ...
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... NXP Semiconductors 11. Static characteristics Table 12. Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V). T Symbol Parameter V HIGH-level output OH voltage V LOW-level output OL voltage I input current I I supply current CC [3] I additional supply CC current C input/output io capacitance [1] All typical values are measured at V [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed ...
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... NXP Semiconductors 12. Dynamic characteristics Table 13. Dynamic characteristics V = 3 Symbol Parameter 1.1 V ref TT t LOW-to-HIGH propagation delay PLH t HIGH-to-LOW propagation delay PHL t LOW to OFF-state propagation delay nBI to nA (I/O); see PLZ t OFF-state to LOW propagation delay nBI to nA (I/O); see PZL ...
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... NXP Semiconductors Table 13. Dynamic characteristics V = 3 Symbol Parameter 1.2 V ref TT t LOW-to-HIGH propagation delay PLH t HIGH-to-LOW propagation delay PHL t LOW to OFF-state propagation delay nBI to nA (I/O); see PLZ t OFF-state to LOW propagation delay nBI to nA (I/O); see PZL [1] All typical values are ...
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... NXP Semiconductors input V ref t PLH output 1.5 V PRR 10 MHz Fig 5. Propagation delay, nBI to nAO input V ref t PLH output V ref Fig 7. 5BI to 7BO1 or 6BI to 7BO2 Fig 9. EN1 to 5A (I/O) or EN2 to 6A (I/O) GTL2007_2 Product data sheet 12-bit GTL to LVTTL translator with power good control ...
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... NXP Semiconductors 13. Test information Fig 10. Load circuit for A outputs Fig 11. Load circuit for B outputs Fig 12. Load circuit for open-drain LVTTL I/O GTL2007_2 Product data sheet 12-bit GTL to LVTTL translator with power good control V I PULSE GENERATOR PULSE GENERATOR V PULSE GENERATOR R = load resistor. ...
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... NXP Semiconductors 14. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 14. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Abbreviations Table 16. Acronym CDM CMOS CPU DUT ESD GTL HBM LVTTL MM PRR TTL VRD ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Data sheet descriptive title changed from “13-bit GTL to LVTTL translator with power good control” ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Function tables . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Application design-in information . . . . . . . . . . 7 9 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics ...