MK157303 Integrated Circuit System, MK157303 Datasheet

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MK157303

Manufacturer Part Number
MK157303
Description
Manufacturer
Integrated Circuit System
Datasheet
Block Diagram
The MK1573 GenClock™ provides genlock timing for
video overlay systems. The device accepts the horizontal
sync (HSYNC) signal as the input reference clock, and
generates a frequency-locked high speed output.
Stored in the device are the multipliers for 16
combinations of popular frequencies for analog and
digital TV and set-top box systems. Frequency-locked
outputs include 1X, 4X, and 8X the subcarrier
frequencies of NTSC and PAL systems, and 27MHz plus
13.5MHz for digital video systems. In most selections,
the chip recovers the HSYNC clock by outputting a low
jitter 50% duty cycle version of HSYNC. Also available is
an inverted recovered HSYNC clock, and a double speed
recovered HSYNC clock.
ICS can customize this device for any other different
frequencies.
MDS1573-03 A
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com
Description
HSYNC
Input Clock
FS0-3
4
VDD
Buffer
Input
2
GND
2
GenClock™ HSYNC to Video Clock
CAP1
Synthesis
Circuitry
1
Control
Clock
and
• Packaged in 16 pin narrow (150 mil) SOIC
• Accepts HSYNC of 15.625kHz or 15.73426kHz
• Highly accurate frequency generation within 1 ppm
• Generates NTSC/PAL subcarrier frequencies, and
• Generates 27MHz and 13.5MHz
• 2X HSYNC clock available
• Recovered HSYNC clock available
• Inverted HSYNC clock available
• 3.3V operation
Features
• Exact ratios stored in the device eliminate the need
for external dividers
4X and 8X of those frequencies
CAP2
OE (all outputs)
Output
Output
Buffer
Buffer
Output
Buffer
CLK1
CLK2
CLK3
MK1573-03
111301

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MK157303 Summary of contents

Page 1

... Input Input Clock Buffer MDS1573-03 A Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com GenClock™ HSYNC to Video Clock Features • Packaged in 16 pin narrow (150 mil) SOIC • Exact ratios stored in the device eliminate the need for external dividers • ...

Page 2

... Frequency Select 3. Determines CLK outputs (with given input) per table above. Type Input output power supply connection MDS1573-03 A Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com GenClock™ HSYNC to Video Clock Output Clocks Decoding Table MK1573-03 (MHz) ...

Page 3

... Most selections have zero ppm error. Some selections have a maximum of 1 ppm synthesis error. MDS1573-03 A Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com GenClock™ HSYNC to Video Clock resistor between CAP1 and CAP2 pin (resistor on CAP2 side), with a parallel low ...

Page 4

... Addresses D, E, and F The recovered clocks are triggered by the falling edge of HSYNC and are delayed by about 100ns. MDS1573-03 A Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com GenClock™ HSYNC to Video Clock HSYNC ...

Page 5

... MK1573-03STR While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. ...

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