w83627thg Winbond Electronics Corp America, w83627thg Datasheet - Page 84

• Manufacturer Part Number: w83627thg
• Description: Winbond Lpc I/o
• Manufacturer: Winbond Electronics Corp America

CR23 (Default 0x00)
CR24 (Default 0s110s1sb)
CR25 (Default 0x00)
Bit 7 - 1 : R
Bit 0
Bit 7
Bit 6
Bit 5 - 3 : Reserved
Bit 2
Bit 1
Bit 0
When trying to make a change to this bit, new value of PNPCVS must be complementary to the old
one to make an effective change. For example, the user must set PNPCSV to 0 first and then
reset it to 1 to reset these PnP registers if the present value of PNPCSV is 1. The corresponding
power-on setting pin is NDTRA (pin 52).
Bit 7 - 6 : Reserved
Bit 5
Bit 4
Bit 3
Bit 2 - 1 : Reserved
Bit 0
: IPD (Immediate Power Down).
down mode immediately.
: Reserved
: CLKSEL
= 0 The clock input on Pin 18 should be 24 Mhz.
= 1 The clock input on Pin 18 should be 48 Mhz.
The corresponding power-on setting pin is SOUTB (pin 83).
: ENKBC
= 0
= 1
This bit is read only, and set/reset by power-on setting pin. The corresponding power-
on setting pin is SOUTA (pin 54).
: Reserved. Must be 1.
: PNPCSV
= 0
= 1
: URBTRI
: URATRI
: PRTTRI
: FDCTRI.
ESERVED
The Compatible PnP address select registers have default values.
The Compatible PnP address select registers have no default value.
KBC is disabled after hardware reset.
KBC is enabled after hardware reset.
.
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When set to 1, it will put the whole chip into power
W83627THF/W83627THG
Publication Release Date: September 26, 2006
Revision 1.2