w83627sf Winbond Electronics Corp America, w83627sf Datasheet
w83627sf
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w83627sf Summary of contents
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... W83627SF WINBOND I/O ...
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... W83627SF Data Sheet Revision History Pages Dates 1 n.a. 2000/09/17 2 All 2000/11/ Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. ...
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... TABLE OF CONTENTS GENERAL DESCRIPTION ---------------------------------------------------------------------------------- 1 PIN CONFIGURATION FOR W83627SF---------------------------------------------------------------- 6 1. PIN DESCRIPTION------------------------------------------------------------------------------------------------------------------------- 7 1.1 LPC INTERFACE -------------------------------------------------------------------------------------------------------------------------- 7 1.2 FDC INTERFACE-------------------------------------------------------------------------------------------------------------------------- 8 1.3 MULTI-MODE PARALLEL PORT ---------------------------------------------------------------------------------------------------- 9 1.4 SERIAL PORT INTERFACE ------------------------------------------------------------------------------------------------------------ 13 1.5 KBC INTERFACE-------------------------------------------------------------------------------------------------------------------------- 15 1.6 ACPI INTERFACE------------------------------------------------------------------------------------------------------------------------- 15 1.7 GAME PORT & MIDI PORT------------------------------------------------------------------------------------------------------------ 16 1.8 GENERAL PURPOSE I/O PORT-------------------------------------------------------------------------------------------------------- 17 1.8.1 General Purpose I/O Port 1 (Power source is Vcc)------------------------------------------------------------------------ 17 1.8.2 General Purpose I/O Port 2 (Power source is Vcc)------------------------------------------------------------------------ 17 1 ...
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... Bank0.Reg2 - Interrupt Status Register (ISR)------------------------------------------------------------------------------- 57 5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) --------------------- 58 5.1.5 Bank0.Reg4 - CIR Control Register (CTR) ---------------------------------------------------------------------------------- 58 5.1.6 Bank0.Reg5 - UART Line Status Register (USR) -------------------------------------------------------------------------- 59 5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ------------------------------------------------------------ 60 W83627SF Publication Release Date: Nov. 2000 - Revision 0.60 ...
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... Register B) Mode = 111----------------------------------------------------------------------------- 73 6.3.10 ecr (Extended Control Register) Mode = all------------------------------------------------------------------------------ 74 6.3.11 Bit Map of ECP Port Registers ------------------------------------------------------------------------------------------------ 75 6.3.12 ECP Pin Descriptions------------------------------------------------------------------------------------------------------------ 76 6.3.13 ECP Operation--------------------------------------------------------------------------------------------------------------------- 77 6.3.14 FIFO Operation-------------------------------------------------------------------------------------------------------------------- 77 6.3.15 DMA Transfers --------------------------------------------------------------------------------------------------------------------- 78 6.3.16 Programmed I/O (NON-DMA) Mode----------------------------------------------------------------------------------------- 78 6.4 EXTENSION FDD MODE (EXTFDD) ------------------------------------------------------------------------------------------------ 78 W83627SF Publication Release Date: Nov. 2000 -III - Revision 0.60 ...
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... SMART CARD CONTROL REGISTER (SCCR, WRITE ONLY AT "BASE ADDRESS + 3")------------------------- 97 11.7 INTERRUPT ENABLE REGISTER (IER, AT "BASE ADDRESS + 4")------------------------------------------------------ 97 11.8 SMART CARD STATUS REGISTER (SCSR, AT "BASE ADDRESS + 5")----------------------------------------------- 98 11.9 EXTENDED CONTROL REGISTER (ECR, AT "BASE ADDRESS + 7")--------------------------------------------------- 99 W83627SF Publication Release Date: Nov. 2000 - ...
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... APPLICATION CIRCUITS ------------------------------------------------------------------------------ 137 15.1 PARALLEL PORT EXTENSION FDD----------------------------------------------------------------------------------------------- 137 15.2 PARALLEL PORT EXTENSION 2FDD --------------------------------------------------------------------------------------------- 138 15.3 FOUR FDD MODE----------------------------------------------------------------------------------------------------------------------- 138 16. ORDERING INSTRUCTION--------------------------------------------------------------------------- 139 17. HOW TO READ THE TOP MARKING ------------------------------------------------------------- 139 18. PACKAGE DIMENSIONS------------------------------------------------------------------------------- 140 W83627SF Publication Release Date: Nov. 2000 - Revision 0.60 ...
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... ISA interface counterpart. Approximately 40 pins are saved in LPC I/O comparing to ISA implementation. With this additional freedom, we can implement more devices on a single chip as demonstrated in W83627SF's integration of Game Port and MIDI Port fully transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration ...
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... Moreover, W83627SF is made to meet the specification of PC2000/PC2001's requirement in the power management: ACPI and DPM (Device Power Management). The W83627SF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices. They are very important for a entertainment or consumer computer ...
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... Support 3-mode FDD, and its Win95/98 driver UART Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 8-bit characters --- Even, odd or no parity bit generation/detection Publication Release Date: Nov. 2000 - 3 - W83627SF PRELIMINARY Revision 0.60 ...
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... Support both interrupt and polling modes Fast Gate A20 and Hardware Keyboard Reset 8 Bit Timer/ Counter Support binary and BCD arithmetic Compatible with IEEE 1284 specification Compatible with IEEE 1284 specification TM -2, Phoenix MultiKey/42 Publication Release Date: Nov. 2000 - 4 - W83627SF PRELIMINARY 16 - customer code Revision 0.60 ...
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... CIR Wake-Up by programmable keys SMART Card Wake-up by SCPSNT On Now Wake-Up from all of the ACPI sleeping states (S1-S5) Smart Card Reader Interface PC/SC T=0, T=1 compliant ISO7816 protocol compliant With 16-byte send/receive FIFOs Programmable baud generator Package 128-pin PQFP Publication Release Date: Nov. 2000 - 5 - W83627SF PRELIMINARY Revision 0.60 ...
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... PIN CONFIGURATION FOR W83627SF 103 S5IN#/GP41 104 STRCTL/GP40 105 GP56/PVIDLIM1 106 GP55/VIDO4 107 GP54/VIDO3 108 GP53/VIDO2 109 GP52/VIDO1 110 GP51/VIDO0 111 GP50/PVIDLIM0 112 SCPSNT/GP74 113 SCIO/GP73 114 VCC 115 SCPWR/GP72/STGP72 116 SCCLK/GP71 117 VSS 118 SCRST#/GP70/STGP70 ...
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... These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host. 32khz clock input , for CIR only W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally can be disabled by bit 7 of L0-CRF0 (FIPURDWN W83627SF PRELIMINARY FUNCTION resistor. The resistor Publication Release Date: Nov. 2000 ...
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... EXTENSION FDD MODE: WD2# This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE: WD2# This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... This pin is for Extension FDD B; its function is the same as the TRAK0# pin of FDC pulled high internally. EXTENSION. 2FDD MODE: TRAK02# This pin is for Extension FDD A and B; its function is the same as the TRAK0# pin of FDC pulled high internally W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... EXTENSION FDD MODE: HEAD2# This pin is for Extension FDD B; its function is the same as the HEAD#pin of FDC. EXTENSION 2FDD MODE: HEAD2# This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS recommended if intends to pull up. (select 4EH as configuration I/O port s address W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Panel Switch Output. This signal is used for Wake-Up system from S5 state. This pin is pulse output, active low. cold Panel Switch Input. This pin is high active with an internal pull down resistor. Battery voltage input W83627SF PRELIMINARY FUNCTION FUNCTION Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Josystick. (Default) General purpose I/O port 1 bit 4. Alternate Function Output:KBC P16 I/O port. Joystick II timer pin. this pin connect to X positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 3. Alternate Function Output:KBC P15 I/O port W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... General purpose I/O port 2 bit 3. Power LED output, this signal is low after system reset. (Default) General purpose I/O port 2 bit 2. 12t Alternate VID input bit 4. General purpose I/O port 2 bit 1. 12t Alternate VID input bit W83627SF PRELIMINARY FUNCTION FUNCTION Publication Release Date: Nov. 2000 Revision 0.60 ...
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... This pin generates the PWROK signal while the VCC come in. (Default) General purpose I/O port 3 bit 1. This pin generates the PWRCTL# signal while the power failure. (Default) General purpose I/O port 3 bit 0. Chpset suspend C status input W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Power on setting pin for selecting functions of GP7. Setting value is latched on the rising edge of POWEROK. This pin is internally pulled down during power on, a 4.7 k intends to pull up. Refer to detailed descrption of CR2C bit W83627SF PRELIMINARY resistor is recommended if resistor is recommended if Publication Release Date: Nov. 2000 ...
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... CRFA in logical device C. General purpose I/O port 5 bit 5. Alternate VID output bit 4. General purpose I/O port 5 bit 4. Alternate VID output bit 3. General purpose I/O port 5 bit 3. Alternate VID output bit W83627SF PRELIMINARY resistor is recommended if resistor is recommended if resistor is Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Dedicated power supply for oscillator. Crystal output 32KHz output clock. 2 +3.3V power supply for driving 3V on host interface. +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. Ground W83627SF PRELIMINARY FUNCTION resistor is FUNCTION FUNCTION Publication Release Date: Nov. 2000 Revision 0.60 ...
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... D[7:0], SA[15:0], DRQ[3:0], DACK#[3:0], TC, IOR#, IOW#, IOCHRDY, IRQs W83627SF LAD[3:0], LFRAME#, PCICLK, LDRQ#, SERIRQ, PME# save The transition from ISA to LPC is transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. Interface pins Publication Release Date: Nov. 2000 - 22 - W83627SF PRELIMINARY No count Revision 0.60 ...
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... W83627SF FDC The floppy disk controller of the W83627SF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports bits/sec data rate ...
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... MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 238.5 S MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 118.5 S Publication Release Date: Nov. 2000 - 24 - W83627SF PRELIMINARY Revision 0.60 ...
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... FDC Core The W83627SF FDC is capable of performing twenty commands. Each command is initiated by a multi- byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. ...
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... Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE Publication Release Date: Nov. 2000 - 26 - W83627SF PRELIMINARY Revision 0.60 ...
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... R ---------------------- N ------------------------ HDS DS1 DS0 - 27 - W83627SF PRELIMINARY D1 D0 REMARKS 1 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: Nov. 2000 ...
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... HDS DS1 DS0 - 28 - W83627SF PRELIMINARY D0 REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: Nov. 2000 ...
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... HDS DS1 DS0 - 29 - W83627SF PRELIMINARY REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after command execution Sector ID information after command execution Publication Release Date: Nov ...
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... HDS DS1 DS0 ---------------------- C ------------------------ ---------------------- H ------------------------ ---------------------- R ------------------------ ---------------------- N ------------------------ ---------------------- C ------------------------ ---------------------- H ------------------------ ---------------------- R ------------------------ ---------------------- N ------------------------ - 30 - W83627SF PRELIMINARY D1 D0 REMARKS 1 0 Command codes The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed D1 D0 ...
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... HDS DS1 DS0 - 31 - W83627SF PRELIMINARY D1 D0 REMARKS 0 0 Command code 0 0 Enhanced controller D0 REMARKS 0 1 Command codes Sector ID information prior to Command execution Data transfer between the FDD and system Status information after ...
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... HDS DS1 DS0 - 32 - W83627SF PRELIMINARY D0 REMARKS 0 1 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: Nov. 2000 ...
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... DS1 DS0 W83627SF PRELIMINARY D0 REMARKS 0 1 Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution D0 REMARKS 1 Command codes Head retracted to Track 0 Interrupt D0 REMARKS 0 Command code ...
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... HDS DS1 DS0 - 34 - W83627SF PRELIMINARY D0 REMARKS 1 1 Command codes D0 REMARKS 1 1 Command codes Head positioned over proper cylinder on diskette D0 REMARKS 1 1 Configure information 0 0 Internal registers written D1 D0 REMARKS 1 1 Command codes Publication Release Date: Nov ...
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... HDS DS1 DS0 ---------------- ST3 ------------------------- ------------- Invalid Codes ----------------- -------------------- ST0 ---------------------- - 35 - W83627SF PRELIMINARY D1 D0 REMARKS 1 0 Registers placed in FIFO REMARKS 1 0 Command Code D0 REMARKS 0 0 Command Code REMARKS 0 0 Command Code Status information about ...
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... Register Descriptions There are several status, data, and control registers in W83627SF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 3.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, ...
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... This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP# output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0# input DIR INDEX - 37 - W83627SF PRELIMINARY WP HEAD TRAK0 STEP F/F DRQ INIT PENDING Publication Release Date: Nov. 2000 Revision 0.60 ...
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... This bit changes state at every rising edge of the RDATA# output pin. WE (Bit 2): This bit indicates the complement of the WE# output pin W83627SF PRELIMINARY MOT EN A MOT RDATA Toggle WDATA Toggle Drive SEL0 Publication Release Date: Nov. 2000 Revision 0.60 ...
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... DSD# (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC# (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected W83627SF PRELIMINARY DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2 Publication Release Date: Nov. 2000 Revision 0.60 ...
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... W83627SF PRELIMINARY 01 select drive B 10 select drive C 11 select drive D Tape sel 0 Tape sel 1 Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 Publication Release Date: Nov ...
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... DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the proce - 41 - W83627SF PRELIMINARY None 1 ...
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... S/W RESET PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) DEFAULT PRECOMPENSATION DELAYS 125 nS 125 nS 125 nS 41.67nS 20 W83627SF PRELIMINARY 2 Mbps Tape drive Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled) Publication Release Date: Nov. 2000 Revision 0.60 ...
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... This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83627SF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. ...
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... During execution of the read data or scan command 0 No error Not used. This bit is always W83627SF PRELIMINARY US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault Publication Release Date: Nov. 2000 ...
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... Reserved for the hard disk controller x During a read of this register, these bits are in tri-state DSKCHG W83627SF PRELIMINARY HIGH DENS DRATE0 DRATE1 DSKCHG DRATE0 DRATE1 NOPREC DMAEN DSKCHG Publication Release Date: Nov. 2000 Revision 0.60 ...
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... This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC Reserved - 46 - W83627SF PRELIMINARY 0 DRATE0 DRATE1 0 DRATE0 DRATE1 NOPREC Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) as logical 1 to transmit and check W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... CTS DSR RI Falling Toggling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit W83627SF PRELIMINARY Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt ...
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... Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character. TABLE 4-2 WORD LENGTH DEFINITION DLS1 DLS0 DATA LENGTH 5 bits 6 bits 7 bits 8 bits - 49 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable CTS , Loopback RI input ( bit 2 of HCR) DCD . In the diagnostic mode this bit is internally - 51 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... UFR are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB) RX FIFO INTERRUPT ACTIVE LEVEL (BYTES W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR Empty TBR empty Handshake status 1. TCTS = 1 3. FERI = W83627SF PRELIMINARY Clear Interrupt - 2. PBER =1 Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1 ...
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... RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI W83627SF PRELIMINARY 16 -1. The output frequency of the Publication Release Date: Nov. 2000 Revision 0.60 ...
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... W83627SF PRELIMINARY Error Percentage between desired and actual ** ** 0.18% 0.099 0.53 Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Receiver Buffer Register (RBR) is equal or larger than the threshold level, (2) RBR occurs time-out if the receiver buffer register has valid data and below the threshold level. Clear to 0 when RBR is less than threshold level from reading RBR. Publication Release Date: Nov. 2000 - 57 - W83627SF PRELIMINARY (2) EN_TMR(Enable Revision 0.60 ...
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... For the input signal, that is through a band pass filter, i.e., the frequency of the input signal is located at this defined range then the signal will be received. Receiver Frequency Select 4~0. Select the receiver operation frequency. Publication Release Date: Nov. 2000 - 58 - W83627SF PRELIMINARY Revision 0.60 ...
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... Received FIFO overrun. Read to clear. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical W83627SF PRELIMINARY 011 Min. Max. 23.4 34 ...
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... Hz which is set to pre-divisor into 13. When set to 0, the pre-divisor is set to 1, that is, the input clock of baud rate generator is set to 24M Hz. Receiving Signal Invert. Write to 1, Invert the receiving signal. Publication Release Date: Nov. 2000 - 60 - W83627SF PRELIMINARY Select internal decoder Revision 0.60 ...
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... Cleared Upon Read. - FIFO Level Value. Indicate that how many bytes are there in the current received FIFO. Can read these bits then get the FIFO level value and successively read RBR by the prior value. Publication Release Date: Nov. 2000 - 61 - W83627SF PRELIMINARY Revision 0.60 ...
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... The percentage error for all baud rates, except where indicated otherwise, is 0.16% Decimal divisor used to Percent error difference between generate 16X clock 2304 1536 1047 857 768 384 192 Note 1 1 Publication Release Date: Nov. 2000 - 62 - W83627SF PRELIMINARY desired and actual ** ** 0.18% 0.099 0.53 Revision 0.60 ...
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... EN_TMR=1, the TMR_I is set to 1. When the counter down count to zero, a new initial value will be re-loaded into timer counter. Description Reserved. Timer High Byte Register. See Bank1.Reg4. Publication Release Date: Nov. 2000 - 63 - W83627SF PRELIMINARY 12 -1 ms. The timer Revision 0.60 ...
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... PARALLEL PORT 6.1 Printer Interface Logic The parallel port of the W83627SF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83627SF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port ...
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... Printer status buffer (Read) 0 Printer control latch (Write) 0 Printer control swapper (Read) 1 EPP address port (R/W) 0 EPP data port 0 (R/W) 1 EPP data port 1 (R/W) 0 EPP data port 2 (R/W) 1 EPP data port 2 (R/ W83627SF PRELIMINARY EXT2FDD PIN EXTFDD ATTRIBUTE --- --- --- INDEX2# I INDEX2# TRAK02# I TRAK02# WP2# ...
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... Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect TMOUT ERROR SLCT PE ACK BUSY ACK# BUSY# stops W83627SF PRELIMINARY signal means the printer has S time-out has occurred on the EPP Publication Release Date: Nov. 2000 Revision 0.60 ...
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... The address port is available only in EPP mode. Bit definitions are as follows STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR ACK W83627SF PRELIMINARY changes from low to high. 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Publication Release Date: Nov. 2000 Revision 0.60 ...
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... PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 - 68 - W83627SF PRELIMINARY PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 IOR# causes an EPP read PD2 PD1 1 1 INIT# AUTOFD# STROBE# ...
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... EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. EPP DESCRIPTION Publication Release Date: Nov. 2000 - 69 - W83627SF PRELIMINARY S have Revision 0.60 ...
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... ECP FIFO (Address) R All Status Register R/W All Control Register R/W 010 Parallel Port Data FIFO R/W 011 ECP FIFO (DATA) R/W 110 Test FIFO R 111 Configuration Register A R/W 111 Configuration Register B R/W All Extended Control Register DESCRIPTION Publication Release Date: Nov. 2000 - 70 - W83627SF PRELIMINARY FUNCTION Revision 0.60 ...
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... These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows W83627SF PRELIMINARY 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE Address/RLE 1 nFault Select PError nAck nBusy Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Bit 2: This bit is output to the INIT# output. Bit 1: This bit is inverted and output to the AFD# output. Bit 0: This bit is inverted and output to the STB# output W83627SF PRELIMINARY strobe autofd nInit SelectIn ackIntEn Direction Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Bit 7: This bit is read-only low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts W83627SF PRELIMINARY IRQx 0 IRQx 1 IRQx 2 intrValue compress Publication Release Date: Nov. 2000 Revision 0.60 ...
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... Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. IRQ resource W83627SF PRELIMINARY . empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Publication Release Date: Nov. 2000 Revision 0.60 ...
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... These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO PD5 PD4 PD3 PError Select nFault Directio ackIntEn SelectIn nErrIntrEn dmaEn serviceIntr - 75 - W83627SF PRELIMINARY NOTE PD2 PD1 PD0 nInit autofd strobe ...
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... ECP Mode. O This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. O This signal is always deasserted in ECP mode W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
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... PeriphAck is low. The most significant bit of the command is always zero. 6.3.13.3 Data Compression The W83627SF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
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... I/O will empty or fill the FIFO using the appropriate direction and mode. 6.4 Extension FDD Mode (EXTFDD) In this mode, the W83627SF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 6-1 ...
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... Extension 2FDD Mode (EXT2FDD) In this mode, the W83627SF changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table6-1. ...
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... KEYBOARD CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83627SF is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer ...
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... Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) Publication Release Date: Nov. 2000 - 81 - W83627SF PRELIMINARY Revision 0.60 ...
Page 89
... Enable Keyboard Interrupt BIT BIT DEFINITION No Error Detected 00 01 Auxiliary Device "Clock" line is stuck low 02 Auxiliary Device "Clock" line is stuck high 03 Auxiliary Device "Data" line is stuck low 04 Auxiliary Device "Data" line is stuck low - 82 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 90
... Pulse only RC(the reset line) low for Command byte is even FUNCTION BIT BIT DEFINITION No Error Detected 00 01 Keyboard "Clock" line is stuck low 02 Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low 03 04 Keyboard "Data" line is stuck high - 83 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 91
... Reserved Reserved Reserved Then, GATEA20 and KBRESET are merged along with Port92 when 5 4 Res. (1) Res. (0) Res. ( W83627SF PRELIMINARY P92EN HGA20 Res. (1) SGA20 PLKBRST Publication Release Date: Nov. 2000 Revision 0 ...
Page 92
... GENERAL PURPOSE I/O W83627SF provides 42 input/output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. These 42 GP I/O ports are divided into seven groups. GP1 is configured through control registers in logical device 7, GP2 in logical device 8, GP3 and GP4 in logical device 9, GP5, GP6, and GP7 in logical device C. Users can configure each individual port input or output port by programming respective bit in I/O selection register (0 = output input) ...
Page 93
... GP20 BIT 1 GP21 BIT 2 GP22 BIT 3 GP23 BIT 4 GP24 BIT 5 GP25 BIT 6 GP26 BIT 7 GP27 BIT 0 GP30 BIT 1 GP31 BIT 2 GP32 BIT 3 GP33 BIT 4 GP34 BIT 5 GP35 BIT 0 GP40 BIT 1 GP41 BIT 2 GP42 - 86 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 94
... GP50 BIT 1 GP51 BIT 2 GP52 BIT 3 GP53 BIT 4 GP54 BIT 5 GP55 BIT 6 GP56 BIT 7 GP57 BIT 0 GP60 BIT 1 GP61 BIT 2 GP62 BIT 3 GP63 BIT 0 GP70 BIT 1 GP71 BIT 2 GP72 BIT 3 GP73 BIT 4 GP74 - 87 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 95
... Figure 8.1 Publication Release Date: Nov. 2000 - 88 - W83627SF PRELIMINARY Revision 0.60 ...
Page 96
... PLUG AND PLAY CONFIGURATION The W83627SF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83627SF, there are twelve Logical Devices (from Logical Device 0 to Logical Device C with the exception of logical device 4 for backward compatibility) which correspond to eleven ...
Page 97
... A warm reset will not affect the configuration registers. 9.1.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83627SF enters the default operating mode. Before the W83627SF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed ...
Page 98
... Enter the extended function mode ,interruptible double-write ;----------------------------------------------------------------------------------- MOV DX,2EH MOV AL,87H OUT DX,AL OUT DX,AL ;----------------------------------------------------------------------------- ; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------- MOV DX,2EH MOV AL,07H OUT DX,AL ; point to Logical Device Number Reg. MOV DX,2FH | Publication Release Date: Nov. 2000 - 91 - W83627SF PRELIMINARY Revision 0.60 ...
Page 99
... MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;------------------------------------------ ; Exit extended function mode ;------------------------------------------ MOV DX,2EH MOV AL,AAH OUT DX, W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 100
... ACPI REGISTERS FEATURES W83627SF supports both ACPI and legacy power managements. management block generates an SMI# interrupt in the legacy mode and an PME# interrupt in the ACPI mode. The new ACPI feature routes SMI# / PME# logic output either to SMI# SMI# / PME# logic routes to SMI# only when both PME_EN = 0 and SMIPME_OE = 1. Similarly, the SMI# / PME# logic routes to PME# only when both PME_EN = 1 and SMIPME_OE = 1 ...
Page 101
... Bit 0: ERDRI. Setting this bit to a logical 1 enables RBR data ready interrupt Enable RBR Data Ready Interrupt (ERDRI) Enable TBR Empty Interrupt (ETBREI) Enable SSR Interrupt (ESSRI) Enabel SCPSNT Interrupt (ESCPTI W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 102
... FIFO interrupt active level reached FIFO Data Timeout Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR Empty TBR empty - 95 - W83627SF PRELIMINARY Clear Interrupt - Read SCSR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1 ...
Page 103
... Bit 0: This bit enables FIFO of Smart Card interface. This bit should be set to a logical 1 before other bits of SCFR are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset RX interrupt active level (LSB) RX interrupt active level (MSB) RX FIFO INTERRUPT ACTIVE LEVEL (BYTES W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 104
... Bit 3: The Smart Card interface interrupt output is enabled by setting this bit to a logic 1. Bit 2 – 0: Reserved. Always 0 when read Parity Bit Enable (PBE) Even Parity Enable (EPE) Baud rate Divisor Latch Access Bit (BDLAB IRQ enable - 97 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 105
... RBR Data Ready (RDR) Overrun Error (OER) Parity Bit Error (PBER) No Stop bit Error (NSER) Silent Byte Detected (SBD) Transmitter Buffer Register Empty (TBRE) Transmitter Shift Register Empty (TSRE ) RX FIFO Error Indication (RFEI W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 106
... SCCLK frequency select bit 1 Internal sampling clock base select bit 0 Internal sampling clock base select bit 1 BASESEL1, BASESEL0 multiplier CLKSEL1, CLKSEL0 SCCLK frequuency 00 1.5 MHz 01 3 MHz 10 6 MHz 11 12 MHz - 99 - W83627SF PRELIMINARY 14x 16x 18x 16x Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 107
... BDLAB = 1) Combining with BASESEL1 and BASESEL0 of ECR, these two bytes of registers provide user all the possible combinations to cover all the available settings regarding clock rate conversion factor and baud rate adjustment factor. Publication Release Date: Nov. 2000 - 100 - W83627SF PRELIMINARY Revision 0.60 ...
Page 108
... RBR Data Overrun Parity Bit Ready Error Error (RDR) (OER) (PBER) SCIO CLKSTP direction Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit 10 - 101 - W83627SF PRELIMINARY Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 0 SCPSNT 0 toggle ...
Page 109
... SERIAL IRQ W83627SF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. ...
Page 110
... Start IRQ0 IRQ1 SMI# IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK# INTA# INTB# INTC# INTD# Unassigned - 103 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 ...
Page 111
... Power down = 1 No Power down Bit 2 : Reserved. Bit 1 : SCPWD. Smart card interface power down enable Power down = 1 No Power down Bit 0 : FDCPWD. FDC power down enable Power down = 1 No Power down Publication Release Date: Nov. 2000 - 104 - W83627SF PRELIMINARY Revision 0.60 ...
Page 112
... Bit Reserved Bit 5 : URBTRI. For UART B device. Bit 4 : URATRI. For UART A device. Bit 3 : PRTTRI. For printer port device. Bit 2 : Reserved. Bit 1 : SCTRI. For Smart Card interface. Bit 0 : FDCTRI. For FDC device. Publication Release Date: Nov. 2000 - 105 - W83627SF PRELIMINARY Revision 0.60 ...
Page 113
... Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ. Bit 0 : DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ. Publication Release Date: Nov. 2000 - 106 - W83627SF PRELIMINARY Revision 0.60 ...
Page 114
... SLP_SX# (pin 73) signal falling edge. Then it is reset by the falling edge of S5# signal (pin 103). *Note: The falling edge of PWRCTL# signal (pin 72) is delayed an additional 5ms from the falling edge of SLP_SX# signal for supporting STR (Suspend To RAM) function. Publication Release Date: Nov. 2000 - 107 - W83627SF PRELIMINARY Revision 0.60 ...
Page 115
... CR2B (GPIO multiplexed pin selection register 2. VCC powered. Default 0xC0) Bit Reserved Bit 5 : PIN90S = 0 PLED (PLED0 control bits are in CRF5 bit Logical Device GP23 Bit 4 : PIN89S = 0 WDTO (Watch Dog Timer is controlled by CRF5, CRF6, CRF7 of Logical Device GP24 Publication Release Date: Nov. 2000 - 108 - W83627SF PRELIMINARY Revision 0.60 ...
Page 116
... GP function initially and switch to Smard Card function. Bit 4-0 : Reserved CR2D (Default 0x00) Test Mode: Reserved for Winbond. CR2E (Default 0x00) Test Mode: Reserved for Winbond. CR2F (Default 0x00) Test Mode: Reserved for Winbond. Publication Release Date: Nov. 2000 - 109 - W83627SF PRELIMINARY Revision 0.60 ...
Page 117
... The internal pull-up resistors of FDC are turned off. Bit 6 : INTVERTZ This bit determines the polarity of all FDD interface signals FDD interface signals are active low FDD interface signals are active high. Publication Release Date: Nov. 2000 - 110 - W83627SF PRELIMINARY Revision 0.60 ...
Page 118
... Forced to logic Forced to logic 0) Bit 1 : DISFDDWR = 0 Enable FDD write Disable FDD write(forces pins WE, WD stay high). Bit 0 : SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not FDD is always write-protected. Publication Release Date: Nov. 2000 - 111 - W83627SF PRELIMINARY Revision 0.60 ...
Page 119
... Bit DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A Select Regular drives and 2.88 format = 01 3-mode drive = 10 2 Meg Tape = 11 Reserved Bit 2 : Reserved. Bit 1:0 : DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. Publication Release Date: Nov. 2000 - 112 - W83627SF PRELIMINARY Revision 0.60 ...
Page 120
... DRVDEN1(pin 3) SELDEN DRATE0 DRATE1 DRATE0 DRATE0 SELDEN DRATE0 DRATE1 - 113 - W83627SF PRELIMINARY SELDEN FM --- 1 250K 1 150K 0 125K 0 --- 1 250K 1 250K 0 125K 0 --- 1 250K 1 --- 0 125K 0 DRIVE TYPE 4/2/1 MB 3.5” “ ...
Page 121
... Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. Publication Release Date: Nov. 2000 - 114 - W83627SF PRELIMINARY Revision 0.60 ...
Page 122
... These two registers select Serial Port 2 I/O base address [0x100:0xFF8 byte boundary. CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit [3:0] : These bits select IRQ resource for Serial Port 2. Publication Release Date: Nov. 2000 - 115 - W83627SF PRELIMINARY Revision 0.60 ...
Page 123
... Active pulse 1.6 S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock - 116 - W83627SF PRELIMINARY IRRX high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX Publication Release Date: Nov ...
Page 124
... Bit Reserved. Bit [3:0] These bits select IRQ resource for KINT (keyboard). CR72 (Default 0x0C if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit [3:0] These bits select IRQ resource for MINT (PS2 Mouse) Publication Release Date: Nov. 2000 - 117 - W83627SF PRELIMINARY Revision 0.60 ...
Page 125
... Select 6MHz as KBC clock input Select 8MHz as KBC clock input Select 12Mhz as KBC clock input Select 16Mhz as KBC clock input. (W83627SF/W83627HF/F-AW can support these 4 kinds of clock input, but W83627SF/ W83627HF/F-PW only support 12MHz clock input) Bit Reserved. Bit Port 92 disable. ...
Page 126
... If a port is programmed input port, then its respective bit can only be read. CRF2 (GP10-GP17 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. Publication Release Date: Nov. 2000 - 119 - W83627SF PRELIMINARY Revision 0.60 ...
Page 127
... When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 (Default 0x00) Bit These bits select IRQ resource for IRQIN1. Bit These bits select IRQ resource for IRQIN0. CRF4 (Reserved) RX FIFO INTERRUPT ACTIVE LEVEL (BYTES 120 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 128
... The corresponding power on setting pin is pin 81 and its value is latched on the rising edge of PWROK. 1: CRF6 is initialized to be 0x0A and CR30 of this logical device is initialized to be 0x01. 0: CRF6 is initialized to be 0x00 and CR30 of this logical device is initialized to be 0x00. Publication Release Date: Nov. 2000 - 121 - W83627SF PRELIMINARY Revision 0.60 ...
Page 129
... If a port is programmed input port, then its respective bit can only be read. CRF2 (GP30-GP35 inversion register. Default 0x00 Bit Reserved) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. Publication Release Date: Nov. 2000 - 122 - W83627SF PRELIMINARY Revision 0.60 ...
Page 130
... Logical Device A (ACPI) CR30 (Default 0x00) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR70 (Default 0x00) Bit Reserved. Bit These bits select IRQ resources for PME . Publication Release Date: Nov. 2000 - 123 - W83627SF PRELIMINARY Revision 0.60 ...
Page 131
... The range of CIR wake-up index register is in 0x20 - 0x2F. CRE2 Keyboard Wake-Up Data Register This register holds the value of wake-up key register indicated by CRE1. This register can be read/written. Publication Release Date: Nov. 2000 - 124 - W83627SF PRELIMINARY Revision 0.60 ...
Page 132
... Password or Hot keys programmed in the registers Any key. Bit 2 : Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This bit is cleared when wake-up event occurs Disable Enable. Bit Reserved. Publication Release Date: Nov. 2000 - 125 - W83627SF PRELIMINARY Revision 0.60 ...
Page 133
... EN_ONPSOUT. Enable to issue a 0.5 s long PSOUT# pulse when system returns from power loss state and is supposed described in CRE4 bit logical device Disable this function Enable this function. Enable WIN98 keyboard dedicated key to wake up system through - 126 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 134
... Bit 0 : URBPME. UART B auto power management enable disable the auto power management functions enable the auto power management functions. Publication Release Date: Nov. 2000 - 127 - W83627SF PRELIMINARY Revision 0.60 ...
Page 135
... SCIRQSTS. Smart Card interface IRQ status. Bit 5 : Reserved. Return zero when read. Bit 4 : WDTIRQSTS. Watch dog timer IRQ status. Bit 3 : CIRIRQSTS. Consumer IR IRQ status. Bit 2 : MIDIIRQSTS. MIDI IRQ status. Bit 1 : IRQIN1STS. IRQIN1 status. Bit 0 : IRQIN0STS. IRQIN0 status. Publication Release Date: Nov. 2000 - 128 - W83627SF PRELIMINARY Revision 0.60 ...
Page 136
... IRQ. PME interrupt due to FDC's IRQ. PME interrupt due to FDC's IRQ. PME interrupt due to UART A's IRQ. PME interrupt due to UART A's IRQ. PME interrupt due to UART B's IRQ. PME interrupt due to UART B's IRQ. Publication Release Date: Nov. 2000 - 129 - W83627SF PRELIMINARY Revision 0.60 ...
Page 137
... IRQIN0's IRQ. PME interrupt due to IRQIN0's IRQ. PME output enable bit. PME will be generated. Only the IRQ status bit is set. PME event will be generated. - 130 - W83627SF PRELIMINARY PME or SMI interrupt for PME event. Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 138
... GP5 is accessible through "base address", GP6 "base address" +1, and GP7 "base address" +2. CRF0 (GP50-GP56 I/O selection register. Default 0x00 Bit 7: Reserved) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. Publication Release Date: Nov. 2000 - 131 - W83627SF PRELIMINARY Revision 0.60 ...
Page 139
... When set to a '0', the incoming/outgoing port value is the same as in data register. CRF9 (VID input data register. Bit Reserved) This register is read only. It contains original VID value. Bit 7 – Reserved. Bit 4 – Original VID value. Publication Release Date: Nov. 2000 - 132 - W83627SF PRELIMINARY Revision 0.60 ...
Page 140
... VID guarding bits specified in bit this register. VID outputs are equal to VID inputs if constraint is not met. Bit 6 Bit 5 Limit constraint units constraint units constraint units constraint - 133 - W83627SF PRELIMINARY Publication Release Date: Nov. 2000 Revision 0.60 ...
Page 141
... +10 LIH I -10 LIL +10 LIH I -10 LIL - 134 - W83627SF PRELIMINARY UNIT V +0 UNIT CONDITIONS 2.5 V BAT 5.0 V, All ACPI pins are SB not connected ...
Page 142
... Output Low Voltage V OL MIN. TYP. MAX. UNIT 0.8 V 2.0 V 0.4 V 2.4 V +10 -10 0.8 V 2.0 V 0.4 V +10 -10 0.8 V 2.0 V 0.4 V 2.4 V +10 -10 0.4 2.4 0.4 2.4 0.4 0.4 - 135 - W83627SF PRELIMINARY CONDITIONS - ...
Page 143
... V 3 LIH I LIL V 0.5 0 1.6 2 0.5 1 LIH I LIL V 0.5 0 1.6 2 0.5 1 LIH I LIL - 136 - W83627SF PRELIMINARY UNIT CONDITIONS ...
Page 144
... DCH2/PD4 18 RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram JP13 - 137 - W83627SF PRELIMINARY JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 20 ...
Page 145
... Parallel Port Extension 2FDD Connection Diagram 15.3 Four FDD Mode W83977F DSA DSB MOA MOB JP13 74LS139 G1 1Y0 A1 1Y1 B1 1Y2 1Y3 2Y0 2Y1 G2 2Y2 2Y3 138 - W83627SF PRELIMINARY JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 ...
Page 146
... W83627SF-AW AM. MEGA. 87-96 821A2B282012345 1st line: Winbond logo 2nd line: the type number: W83627SF-AW 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: the tracking code 821: packages made in '98, week 21 A: assembly house ID; A means ASE, S means SPIL.... etc. ...
Page 147
... Detail F Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 - 140 - W83627SF PRELIMINARY Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom Max A 0.25 0.35 0.45 0.010 0.014 ...